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Re: [Xylo-SDR] Your FPGA Code
This is simply great - I've been reading all the Verilog tutorials I can
find and non of your tips came up in any of them. I am sure that many of us
newbies appreciate the effort that you went to in making these suggestions.
I'm making very good progress with the full implementation of the Wolfson
interface and will have it ready for critique very shortly.
Just a few questions:
I will need to use the 24.576MHz clock from the Wolfson/TI A/D as the means
of changing states. It would be useful to frequency double this to allow
me to add more states in the future if needed. I could use the PLL to do
this but would rather keep this free for something more exciting in the
future. If I were doing this in hardware I would simply use an XOR and delay
the clock to one input, is it this approach sound in an FPGA?
Phil C advised that I need to attach the 24.576MHz clock to pin 66 of the
Xylo FPGA - why can't I use just any pin?
When running a simulation I can choose either Functional or Timing. Until
you pointed out the Functional option I've been using Timing mode which
allows me to generate the simulation waveforms by simply clicking on the
Blue Squarewave button. What are the reasons for the two modes and when
should each be used?
Thanks in advance for your help.
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