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Re: [Xylo-SDR] USB 2.0 in Verilog



And it will eat up huge chunks of ram for the buffers, which might be needed for other uses.

At 06:16 AM 12/21/2005, you wrote:
You need an external PHY with USB2 in FPGA... not really worth it...
use the FX2.

Phil N8VB

On 12/21/05, Leon Heller <leon.heller@bulldoghome.com> wrote:
> I was just looking through the Opencores stuff:
>
> http://www.opencores.org/
>
> and noticed a USB 2.0 core that someone is working on.
>
> Leon
> --
> Leon Heller, G1HSM
> leon.heller@bulldoghome.com
> http://www.geocities.com/leon_heller
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Cecil Bayona
KD5NWA
www.qrpradio.com

"I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ... "