3. I have samples of the new Analog Devices AD9446 16 bit 100 MSPS A/D convertor. I was working with various QSD designs (trying to improve the performance at 18+ MHz), but I have come to the conclusion that this is becoming a waste of time with the new 16 bit high speed converters coming out. I think I am going to change the design of the HPSDR to use this 16 bit 100 MSPS A/D instead of a QSD based design.I will use the Xilinx FPGA to act as a DDC (direct digital down converter -see AD6620). So basically the RX chain will consist of a AD9446 A/D and a Xilinx FPGA! Can't get much simpler than that...... I've got a couple of samples of the similar 14-bit ADCs, I should have ordered the 16-bit ones, instead. The former is really intended for IF processing.
The December '05 QST has a review of the SDR-14, which uses a 14-bit ADC sampling at 66 MHz and an AD6620 DDC. It can give pretty good results, but it does have limitations in an environment where there are many strong signals.
As with any receiver, if you intend to use it in an area where there are likely to be strong out-of-band signals, you really want a tight bandpass filter on the front end, a means to reduce the input level, and a means to match impedances well. The SDR1K is much better with the RFE than without it. On receive, the RFE is really just a collection of better input filters and an impedance-matching preamp.
Enjoy! Lyle KK7P