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Re: [Xylo-SDR] Cyclone II
----- Original Message -----
From: "KD5NWA" <firstname.lastname@example.org>
To: "Xylo-SDR Discussion" <email@example.com>
Sent: Sunday, January 15, 2006 12:55 AM
Subject: Re: [Xylo-SDR] Cyclone II
How many I/O pins will you have left over?
The RAM has 37 connections, leaving 89-37=52 I/Os. I'll bring the shared
pins out to the connector, anyway, so they will be available if the RAM
Ram could be useful if one wants to move some of the number crunching
into the FPGA, specially practical since you are using a model with
multipliers built in.
Are you putting a socket for a extra clock module?