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Re: [Xylo-SDR] FPGA pin names in schematic - Some thoughts...
I'll jump in about here.
Yes! Teamspeak session at 1700 tomorrow if you are desingning please be
We do not need to forget the intent of the project here and put fpga's on
every project board! Defeats the purpose. No reason the fpga can't be
arbitrated to give us the 'best we can do' as Lyle suggests here. Just takes
some negotiation so that all our different gauge tracks meet at the golden
spike! Then throw a turntable in there.
Phil_C designs his radio and interfaces with the FPGA on the buss. Then when
proof of concept is done (even with noise etc.) He rotates the FPGA
heartbeat board clockwise, rotates his radio board counter clockwise, sends
it to the PCB house to flatten it out and plugs it into the Enclosure
horizontally and calls it Phil's HPSDR like he has on his website! The
PhilBill board can do the same thing - Or can just use the prototype case
From: firstname.lastname@example.org [mailto:email@example.com]
On Behalf Of Lyle Johnson
Sent: Friday, January 20, 2006 11:45 AM
To: Xylo-SDR Discussion
Subject: Re: [Xylo-SDR] FPGA pin names in schematic - Some thoughts...
> 1. We have a BUS/USB COMMs board to handle communications over the bus
> and to/from USB. The main function of this board is to control the
> bus and handle communications over the bus. This would be a Cyclone
> II - Cypress FX2 based board like what Leon is designing. It could
> take on other roles as LE space permits.
Do you really need much more than the Cypress USB chip for this? What
role does the FPGA play?
> 2. Since the Cyclone II can do LVDS, maybe we should be looking at
> having only LVDS signals on the motherboard bus. This would require
> that we either use a LVDS capable FPGA/CPLD or a LVDS
> serializer/deserializer chip on each plug in board to talk to this
I suggest that you have some group of backplane pins labeled
"user1..userx" so you don't restrict things to only LVDS. Alternately,
just have a group of perhaps 8 signal pairs defined as LVDS.
You might have some slower signals running around like I2C, SPI, CAN,
JTAG (please to consider the ability to use a JTAG chain across the
backplane), some open collector lines for a wire-ored way to send
interrupt requests around, etc. By limiting the board to only 100mm
square, you are ensuring that most systems will be comprised of multiple
boards. No one has articulated what is being designed yet -- just some
flexible hardware for fun. That being the case, you probably want to
leave your options open.
Stirring the pot,
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