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Re: [Xylo-SDR] Architecture review


I think that we are one the same page. I think that it is time that we produced some block diagrams of what each of the boards will look like. Do we have a shared view of what drawing package to use - I normally use VISIO but happy to use a package that we can all use.

73's  Phil...VK6APH

----- Original Message ----- From: "Bill Tracey" <bill@ewjt.com>
To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Saturday, January 21, 2006 3:04 PM
Subject: Re: [Xylo-SDR] Architecture review


I am not against multiple FPGAs in some of the higher function devices
being contemplated, but want to make sure we've still got the capability to
do a basic function device with the single  FPGA on the backplane.

In my mind a basic function device  is a basic narrow band SDR  or SDR
accessory.     Examples would be a SoftRock style gizmo with a DDS and a
192 KHz sound card replacement board with all control and audio going back
to the PC via the USB cable. 2nd example of this class device is an SDR
1000 sound card replacement, cw helper and frequency corrector/stabilizer
and perhaps PIO replacement.  For this class of devices I'd expect/hope to
use the single FPGA on the backplane for the various functions needed (DDS
control, filter selection, I2C chit chat. reference counting,  and A/D
converter interfacing).  I'd expect to have the A/D clock for the audio
board on it's board, the clock for a DDS on it's board, etc -- but I'd be
looking at doing all of the control for these gizmos from the single
FPGA.   I'd not expect to put an FPGA on the sound card replacement board
for example. In this class of device the sigs I'd expect to see on the
backplane are in the 10's and 100's of khz, with the exception of the
master audio oscillator clock at  24.576 MHz and the master FX2/FPGA
12/24/38 MHz clock.  I don't see anyway avoiding bringing the Audio AD
master clock across the bus as the FPGA will need it if it is to clock data
out of the AD converter.

The 2nd class of device is a wider band device with the fast A/D where one
needs an additional FPGA to do downconversion and decimiation etc.   On
this one the A/D board has it's own clocking and uses the master FPGA/FX2
clock for comms with the FPGA.  In this configuration there may be no need
for a 24.576 MHz audio oscillator to be on the backplane.

So. have I violated the too many HF clocks running around in the basic
configuration with having both the Audio Master Clock and the FPGA/FX2
master clock on the backplane bus?


Bill (kd5tfd)

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