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Re: [Xylo-SDR] Architecture review
3. The only clock signals on the bus are for driving the bus
communications. All other clocks needed for the plug-in boards are
generated locally on that board or use SMA/SMB connectors to jump to
other plug-in boards.
Clearly there will be a need for a master clock eventually when we are
getting serious. The present state of the art in Amateur Radio seems to
be to GPS-discipline a 10 MHz oscillator and use that as the reference
throughout the system. Such a precision-reference can be external (it
may be existing hardware) or could be done on its own board.
Looking at Leons schematic I can see a problem with two separate clocks
for the FPGA and FX2, 50 MHz and 24 MHz. Would we give away too much by
making the FPGA clock 48 MHz?
Both clocks could easily be derived from a 96 MHz clock which I suggest
to be the system Master Clock, GPS locked with a Cupido Reflock.
Actually I have in mind to use a 960 MHz Master clock and divide that
down as required.
For starters we should provide a 48 MHz canned oscillator for the FPGA
with a divide by 2 chip for the FX2. This local clock could later by
bypassed and the 96 MHz clock used via a SMA/SMB connector.
I propose to provide for a 10 MHz reference clock signal on the
backplane. It sure helps to synchronize those clocks.
BTW I have been running the AD9954 DDS chip with a 500 MHz clock here
with success. This only works when the internal PLL is disabled!
So a 480 MHz clock (96 MHz x 5) to drive those AD9954 chips would
certainly be nice.
output to give us a Tx signal. Phil C suggested using a AD9954 for this and
any analogue front ends we may use. I agree that the level of spurs we get
from the NCO are likely to be similar to the AD9954, the latter will be much
easier to implement.
I also support the idea of multiple FPGA's. One that talks to the outside
world (USB, PTT, key etc) and the backplane - i.e. just what Leon is
designing now. If we need others then lets add them on a board-by-board
basis e.g. the LTC2208 should have its own dedicated FPGA and decimate
down to low frequency signals to pass over the backplane.
Multiple high frequecy clocks and signals over the backplane seems like
asking for trouble.
At the moment we have two boards plus the backplane thought throught.
1. USB etc and backplane interface board with Cyclone II FPGA.
2. Sound card replacement board - Wolfson A/D (or TI etc) for Rx I/Q
signals and TVL320 microphone/line input. Dual D/A converters,
speakers/headset and I/Q to QSE. Looks like this board could also do CW
Tx ( I/Q signals and keyer plus sidetone ) if wanted.
3. LTC 2208 with FPGA for Rx. NCO inside FPGA with D/A converter to
provide Tx local oscillator.
4. Ham band BPF board, use bus switches so can be switched into Rx or Tx
chain. HPF's, LPF's, switchable attenuators and preamp(s).
5. Rf board - QSD/QSE with AD9954 DDS and say 1W output ( only use QSD if
we solve NF problems). PIN diode or bus switches for fast Tx/Rx swithcing.
We need to be able to phase modulate the NCO/DDS on Tx at audio rates so we
can use a high efficiency PA design later on.
The LTC board could form the basis of a nice digital scope or spectrum
How are we doing?