Or should I say “Motherboard Woes”.
Cecil, Bill, Steve and I had a pretty long Teamspeak session last Saturday discussing buss speed. What speeds CAN we put on our buss?
None of us really knew! Cecil knew a lot about LVDS and twisted pair, but we don’t have a twisted pair or coax buss! In fact we tried to figure a way to get it into our tiny, cramped, custom designed enclosure, which prompted my departure from the enclosure, buss connectors, etc.
However, the question remains! How DO we design our buss to go the 133 mhz PCI standard or increasing speeds in the later PCI standards. (800 mhz and beyond?) Can we even go 24 mhz to the FPGA, divide by 2 and send it back to the Janus?
My thought was to try to ‘copy’ the PCI standards (Not the connector, just the board spec for the standard). I found again, as I knew before, PCI standards group is a private industry culb with a high price to join. When you get right down to finding out more than the buss labels, there ain’t much but general info. If you take a look at a mother board or even a riser you sure can’t see the innards! There ain’t no schematics ANYWHERE I can find!
I did find some info in a pdf from a PCI Bridge Chip manufacturer, on how to design with their chip which yielded some light on the board design for 133 mhz.
I didn’t have time to read all the stuff and it was a bit beyond me, however I did see one highlight as to how the PCI buss needs to be in order to support high speed design.
The clocks and other “Critical signals” go on the top surface of the board.
This is followed by a groundplane layer.
Followed by the Power supplies layer
Followed by the bottom “Signal” layer (which I took to mean slow speed stuff).
That was pretty ‘sketchy’ but it was the description and perhaps a start. Is this doable for our MB?
I would hate to design and produce a motherboard which couldn’t even pass I2C stuff without causing noise everywhere else. This needs to be versatile and QUIET.
Any suggestions as to where to go with a quiet, high speed MB design?