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Re: [Xylo-SDR] Signal Integrity and Board stackup issues


What are the implications of LVDS on parallel traces on a motherboard. Does
it buy us anything in this context.


-----Original Message-----
From: xylo-sdr-bounces@lists.ae5k.us [mailto:xylo-sdr-bounces@lists.ae5k.us]
On Behalf Of Ray Anderson
Sent: Wednesday, January 25, 2006 11:48 AM
To: xylo-sdr@lists.ae5k.us
Cc: Ray Anderson
Subject: [Xylo-SDR] Signal Integrity and Board stackup issues

There are many things to take into consideration when defining a stackup
for a high-performance system. From a signal integrity perspective these
break down into 3 main categories:

1) Signal Quality and Timing
2) Power Distribution
3) SSO (simultaneous switching outputs) issues

We usually recommend that the power and ground planes be placed as close
as possible to each other in order to minimize the plane pair loop
inductance and keep the power distribution impedance low. 

On a board where you are constrained to just 4 layers this can be
problematic as this forces you to place your signals on the surface
layers. This can have both SI and EMC implications.

Vdd -----

An acceptable alternate stackup (in just 4 layers) might be like so:


Even though the power/gnd plane pairs are now a bit farther apart this
isn't a show stopper for system that don't require an ultra-low power
distribution system impedance. (i.e. an FPGA and a handful of other
ASICS and logic). For High performance CPU boards with 50 to 200 amp
transient currents this wouldn't be a good stackup as the target
impedance would be down in the milliohm range, however for a small
system such as the group is describing it can work well. In this case
you can place the low speed non-critical signals (I2C, control lines and
possibly clocks) on the outer layer. The high-speed data busses can go
on the inner layers.

If you can justify 6-layers then the following stackup might be a good


This provides a good low impedance power distribution system, both
signal layers on internal stripline layers, and perhaps more
importantly, for FPGA applications with lots of output drivers
switching, good balanced return paths to minimize SSO problems.

Besides selecting a good initial stackup there is the issue of PDS
decoupling to address. There are different considerations for core power
as compared for IO power. And different things to be addressed for a
back-plane as compared to a processor board.

I'd be happy to work with the team on these SI issues. At 133MHz you
definitely need to pay attention to SI issues but in the grand scheme of
things, 133 MHz is still a pretty low speed buss compared to what the
industry is dealing with these days.


-Ray   WB6TPU

Raymond Anderson
Senior Signal Integrity Staff Engineer
Product Technology Department
Advanced Package R&D
Xilinx Inc.

Eric wrote:

>However, the question remains! How DO we design our buss to go the 133
>PCI standard or increasing speeds in the later PCI standards. (800 mhz
>beyond?) Can we even go 24 mhz to the FPGA, divide by 2 and send it
back to
>the Janus?


>I would hate to design and produce a motherboard which couldn't even
>I2C stuff without causing noise everywhere else. This needs to be
>and QUIET.


>Any suggestions as to where to go with a quiet, high speed MB design?



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