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Re: [Xylo-SDR] Lionheart Block diagram

----- Original Message ----- From: "Phil Harman" <pvharman@arach.net.au>
To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Thursday, January 26, 2006 8:00 AM
Subject: [Xylo-SDR] Lionheart Block diagram

I've posted a V1.0 of the Lionheart block diagram on www.hamsdr.com in the
public area.

A few questions:

1. How does the FX2 program the FPGA - how many pins do we need to do this
and do they need passing over the DIN bus so we can program other FPGAs via
the USB as well?
2. Why do we need a 50MHz clock for the FPGA why not the 24MHz x 2 from the
FX2 like the Xylo does.
3. I2C - At the moment I've shown the FX2 I2C connections connected to the
FPGA and then from the FPGA to the Bus. Is this what we want?  Perhaps the
FX2 should be an I2C master and the FPGA a slave and the I2C from the FX2
connects to the DIN bus. BUT, Given the problens we have with the Xylo (in
that we can't use the FX2 I2C once we program the FPGA)  perhaps we should
ignore the I2C from the FX2 and implement an I2C master in the FPGA and
include any I2C commands that we want  in the USB protocol.
4. How many pins do we need for the JTAG - how do we pass them over the bus?
5. How many pins for the EPCS1?
6. Part # of 1.2v regulator?
7. Where does LVDS go and how many pins?
8. What type of socket for the 1pps from the GPS - SMB like the 200MHz from
the 200MHz DDS clock on the SDR1000?
9. Where should the USB connector be located - on the front edge of the
board or to a header so it can be mounted on the case back/front panel?
10. Do we need coax sockets on the other clocks?

I've allowed for a 1pps input from a GPS receiver and also a 200MHz input
from the SDR1000 or our own NCO or DDS board so we can do frequency
correction over the USB.

A lot of that stuff is in my original draft schematic:


73, Leon