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Re: [Xylo-SDR] Lionheart Block diagram V1.1

2. To buffer the 200MHz NCO/DDS clock how about an DS90LV018? It only needs 350mV to give 3.3v out and we could place a 50 ohm resistor across the input to terminate the coax correctly.

Note the DC bias requirement for the inputs (easy enough to derive from the 1.2V source for the FPGA with suitable decoupling/filtering) and the common mode limits for the input signals. Also, 200 MHz is the maximum specified frequency for this component.

Lyle KK7P