Generation Report - NCO Compiler MegaCore Function v2.3.0

Entity Namea_nco_st
Variation Namea_nco
Variation HDLVerilog HDL
Output DirectoryC:\Data\HPSDR\trunk\N8VB\OZY_V1\OZY_Verilog_Test\MERC_NCO

File Summary

IP Toolbench is creating the following files in the output directory:
FileDescription
a_nco.vA MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
a_nco_bb.vVerilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.
a_nco.bsfQuartus® II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.
a_nco_st.vGenerated NCO synthesizable netlist. This file is required for Quartus II synthesis. It will be added to your Quartus II project
a_nco.voVerilog HDL IP Functional Simulation model
a_nco_tb.vVerilog HDL Testbench
a_nco_vo_msim.tclModelsim TCL Script to run the Verilog HDL IP Functional Simulation model and generated Verilog HDL testbench in the Modelsim simulation software
a_nco_wave.doModelsim Waveform File
a_nco_model.mMatlab m-file describing a Matlab bit-accurate model.
a_nco_tb.mMatlab Testbench
a_nco.vecQuartus Vector File.
a_nco.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
phi_inc_iINPUT32
fsin_oOUTPUT16
fcos_oOUTPUT16
clkINPUT1
resetINPUT1
clkenINPUT1
data_readyOUTPUT1