HPSDRwiki - User contributions [en]

Mercury - Development History

2010-09-20T01:07:29Z

KK7P: relesed under TAPR OHL

This is the development history of the [[MERCURY|Mercury]] receiver board.

==== Updates 19th September 2010 ====
Mercury is now relesed under the TAPR Open Hardware License.

Schematic posted: http://www.hamsdr.com/dnld.aspx?id=1112

PCB Files posted: http://www.hamsdr.com/dnld.aspx?id=1111

Bill of Materials posted: http://www.hamsdr.com/dnld.aspx?id=1113

==== Updates 25th October 2008 ====
Today I brought my laptop home from work, which enabled me to run separate instances of [[PowerSDR]], one on the laptop, and the other on my home PC. I have two Atlas boards, each with its Ozy. On one of them I have a production Penny module, and the other holds my main station radio which has a version of Mercury FPGA code running in its own Ozy. I have about 18 dB of gain in front of the ADC in this arrangement.

I connected an attenuated version of the Penny output at 1.8 MHz into the Mercury Rx. The input level was set to -3 dBm, or S9+70 dB. I have taken a snapshot of the spectrum, which is shown. There are a couple of close in spurs at around 2 kHz spacing, but these are around 100 dB down.

While transmitting on 1.8 MHz I tuned Mercury to 3.8, 7, and 10 MHz to look at the noise floor. Going from Tx off to Tx on raised the noise floor from -128 dBm to -127 dBm, both with a 500 Hz CW filter active.

I then tuned the Rx back to 1.8 MHz and connected my paddle to the DB9 on Ozy. While sending a string of dits at 25 wpm, I looked at the S meter at spacings of 1, 3, 5, and 10 kHz, checking for key clicks. The dBC readings on the S meter were -60, -80, -90, and -100 respectively.

Does anyone know of any standards against which key clicks are measured? I don't but the results seem pretty good to me. I also think that the close in noise and spurs, and wideband noise are excellent. The combined blocking dynamic range of Mercury, and wide band noise of Penny, show excellent potential for being able to work in close proximity, eg on a DXpedition.

73, Greg, ZL3IX

====Update 20th September 2008====
Alpha 3 Mercury built and passes all performance test. Here is a photo of the board that will be going to manufacture shortly. For price and ordering information see [http://www.hamsdr.com.].

Performance figures are as follows:

ADC overload (preamp on ) -12dBm (preamp off) +8dBm

MDS (500Hz) all bands 160m - 6m = -138dBm (preamp on) - 118dBm (preamp
off)

MDS (500Hz) 6m via Alex preamp = -146dBm

IP3 equivalent = +33dBm (preamp on) >50dBm (preamp off)
The IP3 is independent of tone spacing.

Blocking Dynamic Range 119dB

Blocking Dynamic Range was measured at 100kHz and 5 kHz for 1dB gain
compression with similar results.
The DBR is set by the overload point of the ADC rather than being phase
noise limited.

122.88MHz clock phase noise -149dBc/Hz at 1kHz spacing.

'''Update 11th February 2009''': Added construction documents to the hpsdr website at http://openhpsdr.org/support.html

'''Update 21st September 2008''': Production Rev A Schematic posted: (updated, see above)

'''Update 21t September 2008''': Production Rev A PCB Files posted: (updated, see above)

'''Update 23rd August 2008''': Mercury Alpha 2 prototypes have been tested. A minor issue arose which required a modification to the PCB layout. Alpha 3 PCBs are due Friday August 29th for commercial attachment of the ADC, preamp and FPGA chips. Final assembly of two Alpha 3 prototypes will then be done by the testers and measurements taken. We really hope this is the last PCB turn!

'''Update 10th July 2008''': Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

[[Image:alpha1bareA.gif|thumb|400px|Bare Alpha PCB]]

'''Update 16th April 2008''': Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

'''Update 5th April 2008''': Updated block diagram to represent current schematic.

'''Update 18th March 2008''': TAPR has agreed to fund the Mercury development proposal.

'''Update 24th May 2007''': Block diagram of [[Verilog]] code added.

'''Update 3 May 2007''': Block diagram updated. Lyle KK7P has offered to lay out the PCB.

'''Update 1 April 2007''': Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Production Verilog code

[[Image:Mercury_Verilog(6)_1.jpg]]

[[Image:Mercury_Verilog(6)_2.jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

'''Update 28th December 2006'''.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

'''1th August 2006'''. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

'''15th August 2006'''. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

'''18th June 2006'''. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

[[Category:Mercury]]

MAGISTER

2010-09-19T19:01:15Z

KK7P: design files now relesed under OHL.

[[Image:Magister1.gif|thumb|500px]]
The project leader for the Magister board is Lyle Johnson, KK7P

'''Magister''' is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 19 September 2009).

The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.

===Magister Development History===
[[Image:Magister2.gif|thumb|500px|Magister prototype in operation with Mercury]]
The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code.

Magister was initially released under the TAPR NCL until TAPR hds an opportunity to build an initial quantity and distribute them.

Now that TAPR is sold out, and to support the project while awaiting the GigE-based interface card, Magister is now released under the TAPR Open Hardware License.

Design material are available on hamsdr.
* PCB files: http://www.hamsdr.com/personaldirectory.aspx?id=1108
* Schematic: http://www.hamsdr.com/personaldirectory.aspx?id=1109
* Bill of Materials: http://www.hamsdr.com/personaldirectory.aspx?id=1110

The PCB files are complete, and the entire design is released under the TAPR OHL.

[[Category:Hardware available]]

MAGISTER

2009-09-28T16:11:21Z

KK7P: new file link for PCBs

[[Image:Magister1.gif|thumb|500px]]
The project leader for the Magister board is Lyle Johnson, KK7P

Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 19 September 2009).

The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.

===Magister Development History===
[[Image:Magister2.gif|thumb|500px|Magister prototype in operation with Mercury]]
The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009).

Magister is initially released under the TAPR NCL until TAPR has an opportunity to build an initial quantity and distribute them.

Design material are available on hamsdr.
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=1008
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=1004

Note the PCB files do not include drill information. Once Magister initial production is concluded, the PCB materials will be posted complete, and the entire design will re-released under the TAPR OHL.

Hardware Introduction

2009-09-26T03:58:01Z

KK7P: Corrected Magister-Janus incompatibility claim. At least, I think it is correct now! MInor edit on LPU: (12V signal -> 12V source), indicated only a kit. Corrected torroids -> toroids.

There is sometimes confustion among those new to HPSDR about exactly what hardware you need to be able to play with the system. This guide hopes to dispel some of this confusion and allow you to get up and going. Please note that availability is constantly changing, and while we try to keep this page as up to date as possible, things may have changed.

=Required Components=
==Atlas==
Description: [[Atlas]] is the main bus board for the OpenHPSDR system. it connects all of the components together and allows them to talk to one another. It also provides the connection for the power supply. [[Atlas]] has no real active components on it, merely some LEDs, connectors, capacitors and resistors.

Availability: [[Atlas]] is currently available in kit form from TAPR. You can order this kit off of their [http://www.tapr.org/kits_atlas.html order page]

==Ozy==
Description: [[Ozymandias]] (or Ozy) is the board that connects the HPSDR boards to your PC or Mac. The current version of Ozy connects to your PC using USB 2.0. Future versions of Ozy will connect to your computer via Ethernet.

Availability: [[Ozymandias]] is no longer available in kit form. TAPR does have bare PC boards available on their [http://www.tapr.org/kits_ozy.html order page] so that you can buy parts and assemble it yourself. The parts for Ozy are not difficult to get, and are available from [http://www.mouser.com Mouser] and [http://www.digikey.com DigiKey], but assembly of the board will require some expertise in surface mount soldering. The pins of the Cyclone FPGA and FX2 are very small and require some dexterity and patience to assemble. A project called [[Magister]] is currently in pre-production to replace the [[Ozymandias]] until [[OZYII|Ozy II]] is available. [[Magister]] does not include the DB-25 conenctor and I/O to "drive" an SDR-1000, but is expected to be compatible with [[Janus]] for use in QSD/QSE-based SDR systems. [[Magister]] should be available in assembled form from TAPR, please stay tuned for information about when it's going to be available.

==Mercury==
Description: [[Mercury]] is the HPSDR receiver board. It has another Cyclone FPGA on it, and an Analog to Digital converter to receive signals via RF.

Availability: [[Mercury]] is currently available from TAPR in fully assembled form, or as a bare board on their [http://www.tapr.org/kits_merc.html order page].

==Penelope==
Description: [[Penelope]] is the HPSDR transmitter board. It has yet another Cyclone FPGA, and a Digital to Analog converter to generate the RF signal. Of course, if you only want a receiver, OpenHPSDR works fine without a [[Penelope]].

Availability: [[Penelope]] is not available from TAPR currently in kit form or as a bare board. There is a commercial manufacturer of [[Penelope]] that is making boards under TAPR's Open Hardware License, Gerd, DJ8AY. His boards are being sold in the United States through eBay by the seller.

==Power Supply==
You need some way of providing power to the HPSDR components. You have a few choices here. [[Atlas]] is deigned with a PC-style ATX connector on it. An ATX power supply will work to get you going, although many of these supplies are going to be noisy and impart noise into your receiver. A high quality supply is reccommended for this reason. Alternatively, TAPR offers the [[LPU]] that will take a +12VDC source and provide all the necessary voltages to the [[Atlas]] bus. The [[LPU]] is available as a kit from TAPR's [http://www.tapr.org/kits_lpu.html order page].

=Optional Components=
These four boards should get you a functional HPSDR transceiver that will give you something to play with. That being said, there are optional components that may make your setup much more useful.

==Enclosure==
If you're looking for something pretty to put your setup in, the Atlas is designed to use the same spacing as PCI cards in a PC. This allows you to modify an ATX case to handle it such as is described on this Wiki in the [[The Antec P183 Solution]] page.

Alternatively, the project has designed the [[Pandora]] enclosure which has been intended to hold an [[Atlas]] bus with cards, the [[LPU]] and [[Alexiares]]. [[Pandora]] is currently available from TAPR's [http://www.tapr.org/kits_pandora.html order page]. There are also folks on the list making custom backplanes for [[Pandora]] with different mixes of OpenHPSDR boards.

==RF Amplifier==
[[Penelope]] only outputs 0.5 W, so unless you're really fond of QRP work, this isn't going to be enough for most people. To fill this need the project has designed the [[Pennywhistle]] board. [[Pennywhistle]] will be an RF amplifier designed to work with [[Penelope]] and output approximately 20W. This board is in the final stages of pre-production and will be available from TAPR soon. [[Pennywhistle]] will require some sort of low-pass filter between the output and your antenna to comply with regulations limiting harmonic emissions. See the next section about [[Alexiares]] for a possible solution.

==Filtering==
In order to transmit a clean signal, and to provide some suppression of out-of-band signals into the receiver, a filter bank is useful. The project has designed [[Alexiares]] to serve this role. [[Alexiares]] is in pre-production right now and will be available from TAPR. There is a problem sourcing the toroids needed for the board, and it may be necessary for the hobbyist to wind these and solder them into an otherwise pre-assembled board.

==Antenna Selector==
As it stands, there are separate inputs into [[Mercury]] and [[Penelope]] for antennas. If you wish to share an antenna between transmit and receive, you will need a mechanism to do so. Gerd, DJ8AY, is providing a switching board that he is selling through the [http://shop.ebay.com:80/red_ella/m.html?_dmd=1&_ipg=50&_sop=12&_rdc=1 red_ella] eBay seller. Also, [[Alexiares]] will provider transmit/receive switching on some of its antenna connectors.

This list of optional components is by no means exhaustive. There are many more cool components in the pipeline such as [[Excalibur]]. These are just the large components to get a "working" transceiver to get on the air. Of course, you will need a computer to run [[PowerSDR]], [[KISS Konsole]], or [[Ghpsdr]].

MAGISTER

2009-09-18T16:05:37Z

KK7P: Deleted hanging sentence about FPGA.

''' Magister'''

The project leader for the Magister board is Lyle Johnson, KK7P

Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 19 September 2009).

The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.

[[Image:Magister1.gif]]

Magister Development History

The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009).

Magister is initially released under the TAPR NCL until TAPR has an opportunity to build an initial quantity and distribute them.

Design material are available on hamsdr.
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=1005
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=1004

Note the PCB files do not include drill information. Once Magister initial production is concluded, the PCB materials will be posted complete, and the entire design will re-released under the TAPR OHL.

[[Image:Magister2.gif]]

Magister prototype in operation with Mercury.

MAGISTER

2009-09-18T14:25:53Z

KK7P: Corrected typo.

''' Magister'''

The project leader for the Magister board is Lyle Johnson, KK7P

Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 19 September 2009).

The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.

The FPGA also provides the necessary control logic and data formatting for the Janus board as well serial and parallel interfaces for user defined I/O.

[[Image:Magister1.gif]]

Magister Development History

The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009).

Magister is initially released under the TAPR NCL until TAPR has an opportunity to build an initial quantity and distribute them.

Design material are available on hamsdr.
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=1005
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=1004

Note the PCB files do not include drill information. Once Magister initial production is concluded, the PCB materials will be posted complete, and the entire design will re-released under the TAPR OHL.

[[Image:Magister2.gif]]

Magister prototype in operation with Mercury.

MAGISTER

2009-09-18T14:21:59Z

KK7P: Added links to design materials.

''' Magister'''

The project leader for the Magister board is Lyle Johnson, KK7P

Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 18 September 2009).

The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.

The FPGA also provides the necessary control logic and data formatting for the Janus board as well serial and parallel interfaces for user defined I/O.

[[Image:Magister1.gif]]

Magister Development History

The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009).

Magister is initially released under the TAPR NCL until TAPR has an opportunity to build an initial quantity and distribute them.

Design material are available on hamsdr.
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=1005
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=1004

Note the PCB files do not include drill information. Once Magister initial production is concluded, the PCB materials will be posted complete, and the entire design will re-released under the TAPR OHL.

[[Image:Magister2.gif]]

Magister prototype in operation with Mercury.

MAGISTER

2009-09-18T13:51:40Z

KK7P: Initial description.

''' Magister'''

The project leader for the Magister board is Lyle Johnson, KK7P

Magister is an FPGA based interface controller card that provides a high-speed USB 2.0 interface for the Atlas bus, as well as limited additional I/O lines intended for radio control (e.g., bandswitching, CW paddle and so forth). It uses the same Altera Cyclone II FPGA as Ozy and is capable of running the current Ozy code (as of 18 September 2009).

The USB interface uses a Cypress FX2 chip, supporting full duplex USB communications at > 30MB/s.

The FPGA also provides the necessary control logic and data formatting for the Janus board as well serial and parallel interfaces for user defined I/O.

[[Image:Magister1.gif]]

Magister Development History

The project was undertaken by KK7P in mid-summer 2009. Three prototypes were constructed by early September 2009. Magister loads and runs current HPSDR code. Further testing is underway as this is written (19 September 2009).

Magister is initially released under NCL until TAPR has an opportunity to build an initial quantity and distribute them, after which the design materials will be re-released under OHL.

Design materials will be posted soon.

[[Image:Magister2.gif]]

Magister prototype in operation with Mercury.

File:Magister2.gif

2009-09-18T13:44:39Z

KK7P: Magister in action!

Magister in action!

File:Magister1.gif

2009-09-18T13:43:53Z

KK7P: Prototype Magister

Prototype Magister

HPSDRwiki:Community Portal

2009-09-18T13:28:06Z

KK7P: Added one line description about Magister.

== [[FAQ]] - Frequently Asked Questions ==

This is a new section started to allow asking and hopefully answering questions about HPSDR.

== [[DOC]] - Documentation ==

Summary of current documentation available.

=== [[Quick Startup Guide]] ===

Documents to help users get HPSDR setup and working. Includes firmware upload instructions.

=== [http://openhpsdr.org/support.html Support documentation] ===

Documents for user interested in building boards can be found on the [http://openhpsdr.org/support.html Support] page.

=== [[HPSDR_related_software|Software links]] ===

Links to HPSDR software and resources can be found on the [http://openhpsdr.org/resources.html Resource] page.

Links to the FPGA programming course by Kirk, KD7IRS -- see the [[Verilog]] page.

== [[DOWNLOADS]] - Firmware and Software ==

Links to current firmware and software available.

== [[SYSTEM INTEGRATION]] ==

This section contains information relative to "putting the pieces together".

== [[A complete HPSDR transceiver]] ==

This page provides an example of how to build your own transceiver using HPSDR components and other available hardware and software. It concludes with test measurements that compare the finished transceiver to other commercially available high end transceivers.

== [[The Antec P183 Solution]] ==

This page documents an example of how to build your own transceiver using HPSDR components and other available hardware and software in a traditional a mid-tower PC enclosure. This example system can accommodate all sizes of PC motherboards up to the standard ATX. The system design will also accommodate larger PC power supplies to power RF amplifiers in the 200 - 500 watt range. The large enclosure is configured to provide a HPSDR with maximum performance.

== [[ PowerSDR Keyboard Shortcut List ]] ==

This page lists all the known PowerSDR keyboard shortcuts.

== Individual Project Wiki Pages ==

Click on the NAME of the project to get to its page!

=== [[ALEXIARES]] - RF Preselector ===

Alexiares (or Alex for short) is a set of RF Bandpass filters for use with Mercury or any other SDR.

=== [[ANICETUS]] (Anie) - Preselector ===

A few designs for narrow band preselectors

===[[Antenna Switch|ANTENNA SWITCH]] - by NT-Electronics ===

An antenna switch for use with Penelope and Mercury when Alex is not used, also has optional low Noise RX Amplifier for 6 meters

=== [[ATLAS]] - Backplane ===

The Atlas is a passive backplane that all other modules plug into.

=== [[CYCLOPS]] - Spectrum Analyzer ===

Cyclops is a 0-1 GHz spectrum analyzer with tracking generator support.

=== [[DEMETER]] - Power Supply ===

=== [[EPIMETHEUS]] - General Purpose I/O ===

Epi is a general purpose I/O board for the Atlas bus and includes relays, open collectors, IF switching, etc.

=== [[EXCALIBUR]] - Clock Reference board ===

=== [[GIBRALTAR]] - GPS-disciplined Frequency Standard ===

Gibraltar is a GPS-disciplined frequency standard board.

=== [[HELIOS]] - Helios Small Transmitting Loop Antenna and Controller ===

=== [[HERMES]] - A DUC/DDC Transceiver. ===

=== [[HORTON]] - Receiver Module ===

A receiver module integrating the Janus ADC with a QSD on a board for a version of the HPSDR RX board.

=== [[JANUS]] - ADC/DAC Board ===

The Janus module is a very high performance, dual, full duplex, A/D and D/A converter board.

=== [[KISS Konsole]] - Learning SDR Console ===

The KISS Konsole is a software project to provide a straightforward, well-commented User Interface to Mercury and other modules.

=== [[LPU]] - Simple Linear Power Unit ===

The LPU unit takes power from a regulated power supply and steps it to the input needed by Atlas

=== [[MAGISTER]] - USB 2.0 to Atlas Bus Interface ===

The Magister module is an alternative to OZY.

=== [[MERCURY]] - 0-55 MHz Direct Sampling Receiver ===
Perhaps the most exciting of all modules, Mercury will enable direct sampling of the 0-55 MHz spectrum.

=== [[ODYSSEY]] - Low Power Handheld SDR ===

Odyssey includes a low power SDR based on the QSD, QSE, and a dsPIC33 as the basic radio core.

=== [[OZY]] - HPSDR Host Interface & Control ===

The OZY module is an FPGA based interface controller card providing input and output connections to the real world.

=== [[OZYII]] - (AussieII) - A high speed PC interface. ===

=== [[PANDORA]] - Enclosure ===

=== [[PENELOPE]] - Companion Exciter to Mercury ===

A 1/2 watt DUC(k).

=== [[PENNYWHISTLE]] - 20 Watt RF Power Ampilfier ===

The PennyWhistle takes the RF out put of Penelope and ampilifes it to approximately 20 watts.

=== [[PHOENIX]] - QSD/QSE Receiver/Transmitter Module ===

QSD based HF Receiver, a QSE based HF Exciter and a supporting synthesizer.

=== [[PINOCCHIO]] - Extender Card ===

Pinocchio is an extender card to allow measurements and troubleshooting of an active card in an ATLAS backplane.

=== [[PROTEUS]] - Prototyping Board ===

This is the planned prototyping board.

=== [[SASQUATCH]] - DSP back-end ===

The Sasquatch board is a hardware DSP back-end intended for use by constructors who would like to operate
stand-alone rather than attached to a PC.

=== [[THOR]] - High Efficiency HF Power Amplifier ===

Thor is a high efficiency HF power amplifier using Envelope Elimination and Restoration (ERR) techniques.

== [[Board Designer's Resources]] ==

== [[ANCILLARY]] - Additional "stuff" of interest to HPSDR ==
Some stuff like Norton Amplifier, FPGA VHDL/Verilog ...

== [[EXPERIMENTERS-CORNER]] - Ideas not yet projects ==

== [[ADMINISTRATION-NEWS]] - Messages about HPSDR web, wiki, discussion list ==
__NOTOC__

Apollo - Development Discussion

2009-07-31T05:02:01Z

KK7P: added comment about antenna tuner

[[Image:Apollo rev 0.jpg|thumb|400px|Rev 0 of the Apollo schematic. Click for larger images.]]
The initial [[Apollo]] schematic is available for comment and suggestions are desired. Please place them here or email to the mailing list [mailto:hpsdr@lists.openhpsdr.org hpsdr@lists.openhpsdr.org] or direct email to [mailto:la2ni@online.no Kjell Karlsen]

The original PDF version of the schematic is here: [[media:Apollo_rev_0.pdf|PDF rev 0 Schematic]].

<hr>
Three comments:
#I believe the interface is SPI rather than I2C for the TPIC595 latches.
#74HC14 can be used in lieu of 74HC04. The '14 has Schmitt trigger inputs, might help with noise immunity on the control line(s).
#Suggest considering PIN diode antenna switching instead of a relay (RL15). For those who operate CW QSK, quiet is nice. It's even nice for those who don't :-). [[User:KK7P|KK7P]] 21:22, 14 June 2009 (UTC)
<hr>
Another comment: An Elecraft T-1 could also be accommodated at these power levels as an alternative to the suggested LDG. Disclaimer: I work for Elecraft. [[User:KK7P|KK7P]]

Apollo - Development Discussion

2009-06-14T21:22:43Z

KK7P:

[[Image:Apollo rev 0.jpg|thumb|400px|Rev 0 of the Apollo schematic. Click for larger images.]]
The initial [[Apollo]] schematic is available for comment and suggestions are desired. Please place them here or email to the mailing list [mailto:hpsdr@lists.openhpsdr.org hpsdr@lists.openhpsdr.org] or direct email to [mailto:la2ni@online.no Kjell Karlsen]

The original PDF version of the schematic is here: [[media:Apollo_rev_0.pdf|PDF rev 0 Schematic]].

Three comments:

1) I beleive the interface is SPI rather than I2C for the TPIC595 latches.

2) 74HC14 can be used in lieu of 74HC04. The '14 has Schmitt trigger inputs, might help with noise immunity on the control line(s).

3) Suggest considering PIN diode antenna switching instead of a relay (RL15). For those who operate CW QSK, quiet is nice. It's even nice for those who don't :-) [KK7P]

Apollo - Development Discussion

2009-06-14T21:19:54Z

KK7P: Added two comments.

[[Image:Apollo rev 0.jpg|thumb|400px|Rev 0 of the Apollo schematic. Click for larger images.]]
The initial [[Apollo]] schematic is available for comment and suggestions are desired. Please place them here or email to the mailing list [mailto:hpsdr@lists.openhpsdr.org hpsdr@lists.openhpsdr.org] or direct email to [mailto:la2ni@online.no Kjell Karlsen]

The original PDF version of the schematic is here: [[media:Apollo_rev_0.pdf|PDF rev 0 Schematic]].

Two comments:

1) 74HC14 can be used in lieu of 74HC04. The '14 has Schmitt trigger inputs, might help with noise immunity on the control line(s).

2) Suggest considering PIN diode antenna switching instead of a relay (RL15). For those who operate CW QSK, quiet is nice. It's even nice for those who don't :-) [KK7P]

Talk:PANDORA

2009-06-02T23:59:00Z

KK7P: initial comments about PANDORA

A few notes on my initial PANDORA experience:

1) We need to measure the distance between ATLAS and the LPU and see if we can get threaded male-female #4 spacers of the correct length to attach ATLAS to PANDORA,and provide the correct height to fasten the LPU.

2) The screw to attach ATLAS to PANDORA which goes through the mounting ears of the DIN connector need to be slightly longer than the supplied 1/4" length. I used a pair of 3/8" length screws for this.

3) I used #4 internal tooth lock washers under the four (4) corner screws that attach ATLAS to PANDORA.

4) The Black Oxide coating on the supplied screws rubbed off a bit during normal handling.

5) We need to locate a source for QUIET 90mm or 92mm fans, with vibration-isolating mounts (like rubber grommets?). The fan I am using is too small (80 mm), is secured with only two (2) screws, and the case acts like a sounding board, making this the loudest item in my ham shack! Prior to mounting, the fan was a typical PC case fan which was neither quiet nor loud when sitting on the workbench blowing air across the LPU and Mercury.

de KK7P

PANDORA

2009-06-02T21:39:32Z

KK7P: added photo of production pandora

== Pandora Order Page Open at [http://www.tapr.org/kits_pandora.html TAPR].==

'''24 May''' - John Koster said in a [http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/2009-May/009564.html message] (see the message for other details):

<blockquote>While I'm going to start taking orders, it will be some time before I
actually start shipping. Pandora will start arriving at the office
Tuesday. Once they arrive I'll have to move them to off-site storage (31
boxes on my porch won't fit). Then I will have to find a proper box and
packing material. This is something we haven't done in the 8 years I've
been handling these things for TAPR.</blockquote>

== First Units Shipped! ==

My Pandora enclosure arrived today, 02 June 2009. Here is a photo of it with Mercury and Ozy installed. Mercury is at the left edge so the fan will circulate air across the LTC2208, to which I've also attached a small heatsink. The apparent bulging of the cabinet is optical distortion, not mechanical! de KK7P

[[Image:pandora.gif]]

== PANDORA Mark II UPDATE (13 May 2009) ==
Pandora is now finished and the production order has been placed with the manufacturer. The price will be $99 for TAPR members and $109 for non-members. Shipment will probably begin sometime in June. The TAPR web site is '''not''' ready to take orders yet; that will probably happen sometime after Hamvention.

We will have two HPSDR stations (hopefully talking to each other!) at the TAPR Dayton Hamvention booth this weekend. Both stations are mounted in Pandora prototypes, so stop by and take a look!

== PANDORA Mark II ENCLOSURE CONCEPT (Revised -- 11 March 2009)==

After we learned that Ben Hall had stepped aside from active work on the HPSDR "Pandora" enclosure, Phil Harman VK6APH, Scott Cowling WA2DFI, and John Ackermann N8UR sat down together at the ARRL/TAPR DCC in Chicago (September 2008) and roughed out a basic enclosure that we thought could be designed and gotten into production quickly. John [mailto:jra@febo.com] took the design lead.

Working with a major enclosure manufacturer, we're happy to report that the Pandora "Mark II" design is just about ready for production, and will be offered through TAPR.

Here are some details about the design, followed by some drawings to help you visualize it.

* Dimensions are (approximately) 12.2 inches wide, 8.7 inches deep, and 5.3 inches high (footprint such that an SDR-1000 can sit on top of it)
* Atlas mounts in the center rear with six covered slots for access to card I/O (like slots in a PC case)
* "Hatch" in top cover to allow card access without disassembling the case
* Room for LPU power supply
* Room for Alex filter bank, and rear panel cutouts for Alex connectors
* Numerous cooling vents, and provision for a fan
* About 3 x 12 inches of unused space across the front for additional component mounting (perhaps an amplifier???)
* Made of .062 aluminum for easy drilling; several spare holes already drilled for additional connections
* Nicely painted

Here are some photos of the first unpainted prototype; not all accessory holes are drilled, and there will be a few metalwork corrections, but this shows how the enclosure works:

[[Image:pandora_proto_1_scaled.jpg]]

[[Image:pandora_proto_2_scaled.jpg]]

[[Image:pandora_proto_3_scaled.jpg]]

[[Image:pandora_proto_4_scaled.jpg]]

[[Image:pandora_proto_5_scaled.jpg]]

== Top view, looking down: ==
[[Image:Pandora_Top_inside.png]]

== Rear views: ==
[[Image:Pandora_Iso_Rear-Fan.png]]

[[Image:Pandora_Iso_Rear-Vents.png]]

[[Image:Pandora_Rear.png]]

== OLD PANDORA (MARK I) PAGE BELOW ==

== PANDORA ENCLOSURE CONCEPT ==

The project leader for the Pandora Enclosure is Ben Hall [mailto:kd5byb@bellsouth.net], KD5BYB.

== BACKGROUND ==

The Pandora name is taken from the old story of Pandora’s Box. One particular telling of the story states that Pandora’s Box was a holding vessel for all of the misfortunes of mankind. However, Pandora opened the box and all the misfortunes came out. However, Pandora was able to close the box quickly, and hope stayed inside. It is hoped that since Pandora has let all the evil out of the box with hope remaining inside, our Pandora’s box will have already had all of “smoke” let out, leaving only hope and goodness inside.

The Pandora Enclosure is actually not just a box, but a collection of "building block" like parts that can be utilized in the construction of an enclosure for an HPSDR. Early on, it was determined that each HPSDR user had unique requirements for the enclosure of thier HPSDR. With a "building block" concept, each HPSDR user can chose only the parts they will use from the collection:

=== An End Panel ===

This will be an end panel with slots punched out in a fashion similar to what is on the rear of a desktop computer. It will mate to a Commercial Off-The-Shelf (COTS) enclosure. It will also have provisions to allow Close-Out Strips to be attached as well as having provisions to mount the End Panel to a Bottom Plate.

=== Close-Out Strips ===

These strips will be of several designs. They will act like the metal brackets on the back of a standard desktop computer card - they'll fit the punched out slot in the End Panel and will have openings that match each HPSDR card. Some strips will be "blank," allowing closing out of unused slots.

=== A Bottom Plate ===

The bottom plate will have provisions to accept an Atlas card and provide provisions for mounting the bottom plate to the End Panel, allowing alignment of cards plugged into Atlas with the slots in the End Panel.

== DESIGN GUIDELINES ==

The Pandora design is going to be an attempt to hit a moving target. There are cards currently undergoing design and test as this is being written. Therefore, unfortunately, the Pandora design will somewhat constrain card design. Its hoped that these constraints won’t be too much:

1) Atlas will be the “backplane” card for Pandora.

2) Pandora will accept cards no larger than 100 by 220 mm.

3) Pandora won’t be able to house an amplifier or other card with significant heat dissipation. (Discussions already point to a future power amplifier requiring a power supply in excess of what Atlas can support.)

4) Pandora will try to be as friendly as possible for non-USA HPSDR users. Ideally, this will include selection of a commercial enclosure available outside the USA. If not, the parts will be made as flat as possible for the lowest cost in mailing.

5) Pandora will try and minimize the amount of custom-made parts and focus on what can be obtained off the shelf.

6) Pandora will allow for easy access to the cards contained within with minimal disassembly. It is expected some users will use Pandora to house future HPSDR prototype cards.

7) Pandora will follow the standard HPSDR procedures. It won’t be designed in a vacuum and user input will be sought.

8) Materials chosen will allow for the best possible mix of shielding and easy of modification. Ideally, the outer case will be steel for durability and shielding with the remainder of the parts being aluminum for ease of modification.

9) Of course, it should look nice!

== FUTURE CHALLENGES ==

As Pandora is hitting a moving target, any information on what folks are thinking in the following areas would help:

1) Power consumption / Heat dissipation. So far, with Ozy/Janus, this appears to not be a big deal.

2) Card size. Right now, Ozy/Janus are on the smaller end of the possible sizes for cards. If future cards are going to trend closer to the 220 mm maximum, this would be good to know now.

3) Power supplies. If a pico ITX power supply is used (see www.mini-box.com), very little dedicated space is needed for a power supply. If something larger will be the norm, the enclosure size may have to grow.

== CURRENT STATUS ==

==='''Update, 3 Sept 2007.'''===

Due to work and family commitments, progress on Pandora has slowed down a bit. Thankfully, I got a good block of time today to do some work on the BK-959 Pandora Enclosure. I'm specifically referring to it as the "BK-959" enclosure to prevent confusion with the second concept I referred to in the 26 May 2007 update.

The first thing I completed today was a solid model of the Atlas with an Ozy and Janus installed:

[[Image:AtlasJanusOzyModel.jpg|300x400px|A solid model of Atlas with Ozy and Janus installed.]]

I then started fitting it into the model of the BK-959 case with a tentative slot layout:

[[Image:BK959wAtlasOzyJanus.jpg|300x400px|A solid model of the Ten-Tec BK-959 case with Atlas, Ozy, and Janus installed.]]

As I moved around the Atlas/Janus/Ozy assembly to align the boards with the slots, I noticed a problem. If I centered the DB9 and DB25 connectors on Ozy in the center of the slots, the audio jacks and RJ45 jacks on Janus were off-center. Off-center enough that I think one would have trouble inserting the RJ45 plug into the jack:

[[Image:Dbscentered.jpg|300x400px|DB connectors centered in the slot.]]

Now, if I center the audio jacks on Janus so they are centered and that inserting the RJ45 plug would be easy, the DB connectors are now off-center and I imagine one would have a hard time inserting a USB cable into the USB connector on Ozy:

[[Image:Audioscentered.jpg|300x400px|Audio connectors centered in the slot.]]

Okay, that's something I think I can solve by opening up the width of the slots and with the design of the close-out strips.

'''A question for those of you who have installed an Atlas/Janus/Ozy assembly into a PC case - how did you solve this? I'd really like to hear your ideas, either on the reflector, or to my e-mail address. Did you open the slot widths up?'''

Knowing that I probably could fix the centering issue with wider slots, I started to position the Atlas/Janus/Ozy assembly in the fore/aft direction of the case. I then noticed that Ozy and Janus have differing amounts of connector protrusion:

[[Image:Sideview.jpg|300x400px|Side view of the Atlas/Janus/Ozy assembly showing the different connector protrusions.]]

Obviously, the Ozy board has connectors that protrude the farthest, so they will set the position of the Atlas/Janus/Ozy assembly within the case relative to the plane of the slots on the rear of the case. This will result in the Janus connectors being ever-so-slightly recessed inside the case. It will have to be seen in an actual prototype if this presents any issues.

Ben, KD5BYB.

==='''Update, 26 May 2007.'''===

Progress continues on Pandora. From what I've heard from the folks that manned the HPSDR booth at Dayton Hamvention, a common question was "Got an enclosure?" After some discussion on the reflector, it was decided that Pandora needed to move from the "analysis of alternatives" stage to focusing on a design based on the Ten-Tec BK-959 case. For sure, the Ten-Tec BK-959 isn't perfect. But, it's a good quality case, especially considering that the price for one off the shelf at Ten-Tec is about $50.

The next thing on the "to-do" list for Pandora is to create solid models of the components and the case. This is in progress. Below is a picture of Janus model that is still in the works:

[[Image:Janus model.jpg|300x400px|A solid model of the Janus board, not yet complete.]]

A fellow HPSDR enthusiast who for now wishes to remain anonymous has stepped forward to help generate solid models of the existing HPSDR component boards, so this task should be far shorter than if I were doing it alone.

Ben, KD5BYB.

==='''Update, 23 April 2007.'''===

It's been awhile since an entry has been made here, but progress has not stopped! Have had discussions with Ten-Tec regarding BK-959 shielding - as pointed out on the reflector, Ten-Tec confirms that the BK-959 as-is doesn't ground the top and bottom case halves (clamshells) to the inner peices of the case. They presented a simple modification that would allow this to take place. This modification design as well as another are being evaluated now. Have had lengthy discussions with Buckeye Shapeform regarding their line of cases - so far, they are above the $50 US price target by a factor of two. Have also checked out Lansing enclosures, they too exceed the price target by a factor of two.

The case search will continue, but it appears that even with the problem noted above, the BK-959 case is a viable option. For photo/discussion purposes, a physical model was constructed:

[[Image:Top-Angle.jpg|150x250px|Angled view of BK-959 with Atlas and cards from Ozy/Janus size to 220mm maximum length.]]
[[Image:Top-front.jpg|150x250px|Top front view of BK-959 with Atlas and cards.]]
[[Image:Top.jpg|150x250px|Top view of BK-959 with Atlas and cards.]]
[[Image:Side.jpg|150x250px|Side view of BK-959 with Atlas and cards.]]

Discussion of the Photos Above:

The Atlas card is mounted up about 0.4" (10.5mm or so) from the chassis by small screws. Atlas is located such that the input/output connector edges of the cards are flush with the rear panel. It may be preferable to have the input/output connector edges protrude slightly thru the rear panel (see End Panel disscusion above).

(Note: what is called the front/rear panels here may be reversed in your application, depending if you want the card input/output connectors at the front or rear. This is simply a handy nomenclature for this discussion.)

Two fans are included to give some idea of scale. The fan in the rear of the first three photos is a standard 80mm square computer power-supply fan. The fan laying flat is a slightly smaller, 70mm square fan that is only 15.5mm thick. The fan laying flat shows that there is space under the cards for a fan(s) or card-to-card cabling. The cards installed from left to right are 185mm, Janus, Ozy, 160mm, 185mm, and 220mm.

As can be seen, if the Atlas card is fully populated with 220mm length cards like the one on the far right in the first three photos, there is no room for any sort of controls on the front panel. Yet, if the maximum card length is restricted to 185mm, one has about 1.5" (38.76mm) of front panel control space. For shorter cards, space increases of course.

Ben, KD5BYB.

==='''Update, 2 April 2007.'''===

Have contacted Ten-Tec and confirmed that they do not have non-USA distribution on their fine line of enclosures. Have contacted Buckeye Shapeform and am evaluating their line of cases as another potential source for Pandora; will ask them about non-USA distribution. Received input from several non-USA HPSDR enthusiasts, am exploring cases sold by HiFi in Italy ([http://www.hifi2000.it HiFi2000]) and by Vero and by Schroff (links forthcoming). Any other sources of cases from abroad or from here in the USA are welcome at the e-mail link above! Still working End Panel design, have rough preliminary concept laid out that slots the entire End Panel. Status entry below updated to reflect year 2007 instead of 2006.

Ben, KD5BYB.

==='''Update, 25 March 2007.'''===

Initial entry to HPSDRwiki. Ordered and received prototype of Ten-Tec BK-959 case. Received PDF and AutoCAD drawings of BK-959 from Ten-Tec. Have drawn up and fabricated cardboard mock-ups of the possible sizes of HPSDR cards ranging from 100 mm by 120 mm all the way to the maximum size of 100 mm by 220 mm. Currently working on End Panel design, have expanded design from 6 slots (which matched Atlas exactly) to as many slots as the End Panel will allow. This allows users to use the "extra" slots for expansion. Have inquired with Ten-Tec as to non-USA distribution possibilities. Working on contacting Buckeye Shapeform as another source of enclosures.

Ben, KD5BYB.

File:Pandora.gif

2009-06-02T21:36:21Z

KK7P: Photo of early (first?) Pandora production unit as received at KK7P on 02 June 2009

Photo of early (first?) Pandora production unit as received at KK7P on 02 June 2009

HPSDRwiki:Community Portal

2009-06-01T18:26:33Z

KK7P: Added KISS Konsole to list of links.

== [[FAQ]] - Frequently Asked Questions ==

This is a new section started to allow asking and hopefully answering questions about HPSDR.

== [[DOC]] - Documentation ==

Summary of current documentation available.

=== [[Quick Startup Guide]] ===

Documents to help users get HPSDR setup and working. Includes firmware upload instructions.

=== [http://openhpsdr.org/support.html Support documentation] ===

Documents for user interested in building boards can be found on the [http://openhpsdr.org/support.html Support] page.

=== [[HPSDR_related_software|Software links]] ===

Links to HPSDR software and resources can be found on the [http://openhpsdr.org/resources.html Resource] page.

Links to the FPGA programming course by Kirk, KD7IRS -- see the [[Verilog]] page.

== [[DOWNLOADS]] - Firmware and Software ==

Links to current firmware and software available.

== [[SYSTEM INTEGRATION]] ==

This section contains information relative to "putting the pieces together".

----

== Individual Project Wiki Pages ==

Click on the NAME of the project to get to its page!

=== [[ALEXIARES]] - RF Preselector ===

Alexiares (or Alex for short) is a set of RF Bandpass filters for use with Mercury or any other SDR.

=== [[ANICETUS]] (Anie) - Preselector ===

A few designs for narrow band preselectors

=== [[ATLAS]] - Backplane ===

The Atlas is a passive backplane that all other modules plug into.

=== [[CYCLOPS]] - Spectrum Analyzer ===

Cyclops is a 0-1 GHz spectrum analyzer with tracking generator support.

=== [[DEMETER]] - Power Supply ===

=== [[EPIMETHEUS]] - General Purpose I/O ===

Epi is a general purpose I/O board for the Atlas bus and includes relays, open collectors, IF switching, etc.

=== [[EXCALIBUR]] - Clock Reference board ===

=== [[GIBRALTAR]] - GPS-disciplined Frequency Standard ===

Gibraltar is a GPS-disciplined frequency standard board.

=== [[HELIOS]] - Helios Small Transmitting Loop Antenna and Controller ===

=== [[HERMES]] - A DUC/DDC Transceiver. ===

=== [[HORTON]] - Receiver Module ===

A receiver module integrating the Janus ADC with a QSD on a board for a version of the HPSDR RX board.

=== [[JANUS]] - ADC/DAC Board ===

The Janus module is a very high performance, dual, full duplex, A/D and D/A converter board.

=== [[KISS Konsole]] - Learning SDR Console ===

The KISS Konsole is a software project to provide a straightforward, well-commented User Interface to Mercury and other modules.

=== [[LPU]] - Simple Linear Power Unit ===

The LPU unit takes power from a regulated power supply and steps it to the input needed by Atlas

=== [[MERCURY]] - 0-55 MHz Direct Sampling Receiver ===

Perhaps the most exciting of all modules, Mercury will enable direct sampling of the 0-55 MHz spectrum.

=== [[ODYSSEY]] - Low Power Handheld SDR ===

Odyssey includes a low power SDR based on the QSD, QSE, and a dsPIC33 as the basic radio core.

=== [[OZY]] - HPSDR Host Interface & Control ===

The OZY module is an FPGA based interface controller card providing input and output connections to the real world.

=== [[OZYII]] - (AussieII) - A high speed PC interface. ===

=== [[PANDORA]] - Enclosure ===

=== [[PENELOPE]] - Companion Exciter to Mercury ===

A 1/2 watt DUC(k).

=== [[PENNYWHISTLE]] - 20 Watt RF Power Ampilfier ===

The PennyWhistle takes the RF out put of Penelope and ampilifes it to approximately 20 watts.

=== [[PHOENIX]] - QSD/QSE Receiver/Transmitter Module ===

QSD based HF Receiver, a QSE based HF Exciter and a supporting synthesizer.

=== [[PINOCCHIO]] - Extender Card ===

Pinocchio is an extender card to allow measurements and troubleshooting of an active card in an ATLAS backplane.

=== [[PROTEUS]] - Prototyping Board ===

This is the planned prototyping board.

=== [[SASQUATCH]] - DSP back-end ===

The Sasquatch board is a hardware DSP back-end intended for use by constructors who would like to operate
stand-alone rather than attached to a PC.

=== [[THOR]] - High Efficiency HF Power Amplifier ===

Thor is a high efficiency HF power amplifier using Envelope Elimination and Restoration (ERR) techniques.

== [[Board Designer's Resources]] ==

== [[ANCILLARY]] - Additional "stuff" of interest to HPSDR ==
Some stuff like Norton Amplifier, FPGA VHDL/Verilog ...

== [[EXPERIMENTERS-CORNER]] - Ideas not yet projects ==

== [[ADMINISTRATION-NEWS]] - Messages about HPSDR web, wiki, discussion list ==
__NOTOC__

KISS Konsole Requests

2009-06-01T18:21:11Z

KK7P: added request for mouse wheel tuning and locked spectrum display modes.

'''KISS Konsole - Feature Requests'''

1. Enable Number Pad input of frequency - DONE (just made V1.0.0 release!).

2. Allow decimal point input when using Number Pad for frequency input.

3. Add frequency scale to bandscope when wide band display is active.

4. Provide support for Penelope.

5. S Meter.

6. Add Mouse wheel tuning.

7. Add provision to "lock" spectrum and tune Mercury (and Penelope) within that window. This would conceptually be something like the second receiver function in PowerSDR. This could be useful, for example, in a CW contest where you don't want the spectrum display to move around when you pounce on another station. Or a RTTY contest, where you just want to see the data sub-band,or SSB...

PENELOPE

2008-11-13T00:54:25Z

KK7P: removed non-commercial use restriction from Penelope licensed material.

==PENELOPE - Companion Exciter to Mercury==

12th November 2008 = Removed non-commercial restriction from licensed materials, available on hamsdr.
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=910
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=909

23rd May 2008 - Production board - Wide band spurious output by John N8UR. Penelope producing 0.25w out on 14.1MHz

[[Image:penny-5.png]]

23rd May 2008 - Production Board - Phase noise plot by John N8UR. Penelope producing 0.25w out on 14.1MHz and phase locked to on board 10MHz TCXO.

[[Image:penny-spectrumplot.png]]

14th November 2007 - Wide band noise floor measured by Greg, ZL3IX, at -147dBc/Hz. Design sign off and ready for production.

28th September 2007 - Measurements commenced. Below is screen shot showing IMD performance at 0.5w output on 20m (Image by Greg, ZL3IX)

[[Image:14MHzIMD.GIF]]

3rd September 2007 - Added photo of assembled Alpha 2 board

1st September 2007 - Alpha 2 PCB assembled and tested 100% OK - VK6APH

15th August 2007 - Alpha 2 kits all shipped today.

11th August 2007 - Alpha 2 kits are ready to ship except for three (3) parts due on the 14th. Added photos of bare boards (below).

2nd August 2007 - Alpha 2 files uploaded. Alpha 2 parts have been ordered and kits are expected to ship out by the 15th of this month. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=639
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=638
:Costed BOM : had errors, deleted

12th May 2007 - Updated Verilog block diagram.

7th May 2007 - Added ALC code, updated Verilog block diagram.

3rd May 2007 - Alpha PCB working, V2 PCB presently being layed out, block diagram updated to reflect latest changes.

19th April 2007 - Alpha 1 kits sent to Penelope testers!

14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : see August 2nd, above.
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : see August 2nd, above. 
:Initial PCB Layout posted here: see August 2nd, above.
:Initial BOM posted here: see August 2nd, above. 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v11.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Assembled Alpha 2 Board

[[Image:Penny.jpg]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cut trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

23rd April 2007: 
:U31 pin 3 not connected to 3V3. Jumper to U36.
:L27 doesn't pick up 3V3. Jumper to U36.
:U11 pin 2 not grounded. Jumper to C41 or C50.
:PCB silkscreen doesn't show pin 1 on Hittite switches. U9 - lower left. U12 - upper right. Right hand bank of filter switches: lower right. Left hand bank of filter switches: upper left.

MERCURY

2008-09-21T18:01:25Z

KK7P: updated links for pcb and sch

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

Update 20th September: Alpha 3 Mercury built and passes all performance test. Here is a photo
of the board that will be going to manufacture shortly. For price and ordering information see
www.hamsdr.com.

[[Image:Merc-v3.JPG]]

Performance figures are as follows:

ADC overload (preamp on ) -12dBm (preamp off) +8dBm

MDS (500Hz) all bands 160m - 6m = -138dBm (preamp on) - 118dBm (preamp
off)

MDS (500Hz) 6m via Alex preamp = -146dBm

IP3 equivalent = +33dBm (preamp on) >50dBm (preamp off)
The IP3 is independent of tone spacing.

Blocking Dynamic Range 119dB

Blocking Dynamic Range was measured at 100kHz and 5 kHz for 1dB gain
compression with similar results.
The DBR is set by the overload point of the ADC rather than being phase
noise limited.

122.88MHz clock phase noise -149dBc/Hz at 1kHz spacing.

Update 21st September 2008: Production Rev A Schematic posted: http://www.hamsdr.com/dnld.aspx?id=891

Update 21t September 2008: Production Rev A PCB Files posted: (contains design review details, but incomplete manufacturing data pending first Mercury production) http://www.hamsdr.com/personaldirectory.aspx?id=892

Update 23rd August 2008: Mercury Alpha 2 prototypes have been tested. A minor issue arose which required a modification to the PCB layout. Alpha 3 PCBs are due Friday August 29th for commercial attachment of the ADC, preamp and FPGA chips. Final assembly of two Alpha 3 prototypes will then be done by the testers and measurmeents taken. We really hope this is the last PCB turn!

Update 10th July 2008: Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-09-20T17:45:41Z

KK7P: updated schematic and PCB files

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

Update 20th September: Alpha 3 Mercury built and passes all performance test. Here is a photo
of the board that will be going to manufacture shortly. For price and ordering information see
www.hamsdr.com.

[[Image:Merc-v3.JPG]]

Performance figures are as follows:

ADC overload (preamp on ) -12dBm (preamp off) +8dBm

MDS (500Hz) all bands 160m - 6m = -138dBm (preamp on) - 118dBm (preamp
off)

MDS (500Hz) 6m via Alex preamp = -146dBm

IP3 equivalent = +33dBm (preamp on) >50dBm (preamp off)
The IP3 is independent of tone spacing.

Blocking Dynamic Range 119dB

Blocking Dynamic Range was measured at 100kHz and 5 kHz for 1dB gain
compression with similar results.
The DBR is set by the overload point of the ADC rather than being phase
noise limited.

122.88MHz clock phase noise -149dBc/Hz at 1kHz spacing.

Update 20th September 2008: Production Rev A Schematic posted: http://www.hamsdr.com/dnld.aspx?id=890

Update 20th September 2008: Production Rev A PCB Files posted: (contains design review details, but incomplete manufacturing data pending first Mercury production) http://www.hamsdr.com/personaldirectory.aspx?id=889

Update 23rd August 2008: Mercury Alpha 2 prototypes have been tested. A minor issue arose which required a modification to the PCB layout. Alpha 3 PCBs are due Friday August 29th for commercial attachment of the ADC, preamp and FPGA chips. Final assembly of two Alpha 3 prototypes will then be done by the testers and measurmeents taken. We really hope this is the last PCB turn!

Update 10th July 2008: Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-08-24T14:29:27Z

KK7P: repalced PCB Gerbers to reflect rev XA12 (Alpha 3 PCB)

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 24th August: Alpha XA12 Schematic (corresponds to Alpha 3 PCB) posted: http://www.hamsdr.com/dnld.aspx?id=875

Update 24th August 2008: Alpha 3 PCB Files (corresponds to Alpha XA12 Schematic) posted: (contains design review details, but not complete manufacturing data pending board testing pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=876

Update 23rd August 2008: Mercury Alpha 2 prototypes have been tested. A minor issue arose which required a modification to the PCB layout. Alpha 3 PCBs are due Friday August 29th for commercial attachment of the ADC, preamp and FPGA chips. Final assembly of two Alpha 3 prototypes will then be done by the testers and measurmeents taken. We really hope this is the last PCB turn!

Update 10th July 2008: Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-08-24T14:22:52Z

KK7P: deleted link to schematic XA9, added link to schematic XA12

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 24th August: Alpha XA12 Schematic posted: http://www.hamsdr.com/dnld.aspx?id=875

Update 23rd August 2008: Mercury Alpha 2 prototypes have been tested. A minor issue arose which required a modification to the PCB layout. Alpha 3 PCBs are due Friday August 29th for commercial attachment of the ADC, preamp and FPGA chips. Final assembly of two Alpha 3 prototypes will then be done by the testers and measurmeents taken. We really hope this is the last PCB turn!

Update 10th July 2008: Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

Update 19th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: (contains design review details, but not complete manufacturing data pending board testing pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=831

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-08-24T00:50:35Z

KK7P: added update about Alpha 3.

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 23rd August 2008: Mercury Alpha 2 prototypes have been tested. A minor issue arose which required a modification to the PCB layout. Alpha 3 PCBs are due Friday August 29th for commercial attachment of the ADC, preamp and FPGA chips. Final assembly of two Alpha 3 prototypes will then be done by the testers and measurmeents taken. We really hope this is the last PCB turn!

Update 10th July 2008: Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

Update 19th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: (contains design review details, but not complete manufacturing data pending board testing pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=831

Update 19th June 2008: Alpha XA9 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=830

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-07-10T19:14:21Z

KK7P: added July 10 note.

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 10th July 2008: Mercury Alpha 2 prototypes were commercially assembled as a test run for release. One minor problem was found on a PCB footprint and has been fixed in the layout. The boards have passed functional testing (thank you, Scotty!) and are enroute to the Alpha test team!

Update 19th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: (contains design review details, but not complete manufacturing data pending board testing pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=831

Update 19th June 2008: Alpha XA9 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=830

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-06-20T02:06:16Z

KK7P: pcb and schematic file updates

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 19th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: (contains design review details, but not complete manufacturing data pending board testing pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=831

Update 19th June 2008: Alpha XA9 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=830

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-06-12T01:28:15Z

KK7P:

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 11th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: (temporarily withdrawn pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=828

Update 11th June 2008: Alpha XA9 Schematic posted: ( temporarily withdrawn pending changes) http://www.hamsdr.com/personaldirectory.aspx?id=826

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-06-11T22:46:09Z

KK7P: revised link for latest pcb files.

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 11th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: http://www.hamsdr.com/personaldirectory.aspx?id=828

Update 11th June 2008: Alpha XA9 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=826

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-06-11T17:19:26Z

KK7P: updated schematic and pcb file links

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 11th June 2008: Rev B PCB Files (corresponds to Alpha XA9 Schematic) posted: http://www.hamsdr.com/personaldirectory.aspx?id=827

Update 11th June 2008: Alpha XA9 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=826

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-04-27T00:42:48Z

KK7P: Changed PCB files.

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 26th April 2008: Alpha 2 PCB Files posted: http://www.hamsdr.com/personaldirectory.aspx?id=796

Update 8th April 2008: Final Alpha 1 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=781

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-04-16T22:34:31Z

KK7P: Added lapha pcb photo

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 16th April 2008: Alpha PCBs and parts kits arrived. Here is a photo of the bare PCB:

[[Image:alpha1bareA.gif]]

Update 8th April 2008: Final Alpha 1 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=781

Update 8th April 2008: Alpha 1 PCB Files posted: http://www.hamsdr.com/personaldirectory.aspx?id=782

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

File:Alpha1bareA.gif

2008-04-16T22:29:49Z

KK7P: Alpah 1 PCB, unpopulated.

Alpah 1 PCB, unpopulated.

MERCURY

2008-04-08T16:55:18Z

KK7P: updated schematic and added pcb links.

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 8th April 2008: Final Alpha 1 Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=781

Update 8th April 2008: Alpha 1 PCB Files posted: http://www.hamsdr.com/personaldirectory.aspx?id=782

Update 5th April 2008: Updated block diagram to represent current schematic.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v6.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-04-03T03:02:14Z

KK7P: replaced alpha scematic link

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 2nd April 2008: Updated Alpha Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=779

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v5.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

MERCURY

2008-03-19T01:37:07Z

KK7P: added link to alpha schematic

==MERCURY - 0-30MHz Direct Sampling Receiver==

The project leaders for the Mercury board are Phil Harman, VK6APH and Philip Covington [mailto:p.covington@gmail.com], N8VB. The Mercury design will incorporate many design features of the QuickSilver QS1R [http://pcovington.blogspot.com/] prototype also designed by Philip Covington, N8VB.

Perhaps the most exciting of all the modules, the Mercury board will enable direct sampling of the 0-65MHz spectrum. Based on a Linear Technology LTC2208 130MSPS 16-bit A/D converter [http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1155,C1001,C1150,P13693,] the board will contain it's own FPGA to undertake Digital Down Conversion (DDC) to 250 kSPS or less for transfer over the Atlas bus to the USB interface on the OZY board.

MERCURY will downsample in its own Altera Cyclone III FPGA, not unlike the USRP [http://www.comsec.com/wiki?UniversalSoftwareRadioPeripheral].

There will be an option to upgrade to the LTC2209 170 MSPS 16 bit converter from Linear Technology.

Update 18th March 2008: TAPR has agreed to fund the Mercury development proposal.
Initial Alpha Schematic posted: http://www.hamsdr.com/personaldirectory.aspx?id=774

Update 24th May 2007: Block diagram of Verilog code added.

Update 3 May 2007: Block diagram updated. Lyle KK7P has offered to lay out the PCB.

Update 1 April 2007: Block diagram added to Wiki.

Block diagram of Alpha design

[[Image:Mercury_v5.jpg]]

Block diagram of Prototype Verilog code

[[Image:Mercury_Verilog(4).jpg]]

This is a photo of an LT2208 evaluation board connected to an Ozy board. (The little board to the right is a 3.3v regulator)

[[Image:Lt2208-to-Ozy.jpg]]

[[Image:Mercury 3.jpg]]

[[Image:OZY_MERC_TEST.JPG]]

(Above) Initial Mercury prototype by Phil Covington, N8VB

[[Image:MercSpecCIC.gif]]

(Above) Mercury spectrum analyzer software written by Phil Covington, N8VB

Update 28th December 2006.

The V2 Ozy board has double the number of LEs of the previous board so provides a little more room to experiment with the CIC filters. I've managed to fit a 4 section decimate by 512 CIC filter in the FPGA that provides an approximately 195kHz 24bit data stream to PowerSDR. By making the data stream compatible with PowerSDR we can use all the features of that code to evaluate the LT2208. Bill, KD5TFD, added code to PowerSDR to send the current frequency over the USB link to Ozy and that is decoded and applied to the CORDIC NCO in Mercury. That way when PowerSDR is tuned Mercury follows.

As per the calculations below the LT2208 does not require a preamp below 20m. I added a 20dB preamp for the higher bands. At the moment I'm using my ATU as the only form of input filtering and so far there appears to be no strong signal problems.

Today I added a PWM DAC to the FPGA that operates at approximately 48kHz. This allows me to listen to the output of the receiver. My initial reactions are that this is going to be a very good receiver! Whilst the CORDIC NCO spurs are a little higher than I would like there are very large sections of all bands where there a no spurs at all. We have a volunteer working on improving the spur performance. Due to the large number of LEs needed in the FPGA to get acceptable filtering performance we are evaluating alternative technologies to implement the DDC.

Phil...VK6APH

Merc Spec/Scope added Sept 7, 2006

1th August 2006. Preliminary measurements are as follows:

Maximum input level = +9dBm
MDS(500Hz BW) = -120dBm

Since the input transformer on the evaluation board is 1:1 then these results agree with Nyall's calculations below.

15th August 2006. Many thanks to Nyall Davies, G8IBR for providing these calculations. Nyall has many years experience in developing DSP based radar systems and his input and expertise is greatly appreciated.

Mercury - Theoretical Performance

LT2208 clocking at 100 MHz
Input level 1.5 Volts peak to peak mode.
SFDR is quoted as 100 dB typical from 5 to 30 MHz. This figure will be used for IP3 calculations.
Input impedance - balanced 200 Ohm.

IP3 of A/D converter

Thus input power 1.5 dBm for full scale. The A/D is specified at -1 dB full scale, i.e. 0.5 dBm. At this power the maximum third order spurious is 0.5 - 100 = 99.5 dBm From the IP3 diagram the IP3 is 50.5 dBm (54 with 2.25 Vpp input)

Noise figure of A/D converter

The signal to noise ratio of the A/D converter is typically 75.2 dB at 30 MHz and 75.3 at 5 MHz suggesting that we can take it as being evenly spread across the sampling bandwidth. Normally with a single A/D the Nyquist bandwidth is half the sampling frequency but we will be generating phase and quadrature signals so the noise is spread across the full sampling bandwidth. (It can be thought of as 2 samples.) the noise then will be bandwidth limited in the signal processing thus reducing the noise referred back to the input of the A/D by the ratio of the sampling bandwidth to the final bandwidth.

For an SSB bandwidth the noise referred A/D input

= -75.2 dB below -1 dB FS - 10 Log(100 MHz/2.4 kHz)
= -122.4 dBm

Now KTB is -140 dBm thus the noise figure at the A/D input

= 17.6 dB

For 500 Hz bandwidth the noise referred to A/D input

= -75.2 -1 - 10 Log(100MHz/500 Hz)
= -129.2 dB

Thus the noise figure is the same as noise figure is not a function of bandwidth.

LOSSES - NOTE this has assumed no signal processing losses. Signal processing losses will add directly to the noise figure. These could consist of filter weighting loss, truncation losses and clock and A/D jitter.

'''LOSSES'''

Mixer. The digital mixer will have an insertion loss of 3.9 dB so the numbers in the processing will be that amount lower than those coming out of the A/D. Normally there is a 3 dB signal to noise loss due to the image noise from the front end amplifier. As we will be sampling I & Q we will effectively have an image rejection mixer thus no S/N loss is put in for the mixer.

Clock and A/D jitter

The aperture jitter of the LT2208 is 70 fs or 0.07 picoseconds For the sake of fairness we will allow the clock jitter to match the A/D aperture jitter. This can be translated into SSB phase noise and requires an oscillator as follows

300 Hz off carrier -110 dBc/Hz
2000 Hz off -139 dBc/Hz
5000 Hz off -142 dBc/Hz

This is not unreasonable for a good crystal oscillator. The effect is worse at higher frequencies according to the formula

SNR=20 Log(2 pi fin trms)

Where fin is the input frequency and trms is the rms aperture jitter.

This works out at 95 dB at 30 MHz. This appears somewhat meaningless, as the noise distribution will follow the spectrum of the clock. It does mean that we will have an effect similar to reciprocal mixing that will be worst at 10 m.

Truncation losses should not be a problem with a 32 bit system but the word growth in the CIC filters is large. (Number of stages raised to the power of the decimation. As these are usually equal it is NN.) This means that several filters with lower numbers of stages and decimation ratio are usually cascaded and lower bits dropped off.

Weighting loss would appear to be negligible with FIR filters giving one output sample for each input sample but if used for decimation with one output for every input there may be a weighting loss. I will presume that there are no S/N losses associated with the CIC filters, as I can find no reference to them but I have some reservations.

If FFT processing is used, a weighting loss can be calculated.

Without knowing the algorithms I would suggest from experience and gut feeling that we should think in terms of adding 3 dB to the previously calculated noise figure and call it 20.6 dB at the A/D. Allowing 2 dB for the front end filters and 0.8 dB for filter switching we have a noise figure of 23.4 dB.

If we ensure that the external received noise is 10 dB about the Rx noise, the internal noise will only add 0.46 dB to the received noise floor.

Given the suggested figures for minimum atmospheric noise we get the following requirements for a front end.

Band Ext noise dB above KTB Noise figure dB
80 38 28
40 33 23
20 28 18
15 23 13
10 18 8

A front end amplifier with a gain of 15 dB and a 3 dB noise figure will give a final noise figure of 10.3 dB at 30 MHz. (See spreadsheet [link here when I learn how to do it! VK6APH ]).

If it can achieve an INPUT IP3 of 35 dBm, this would match the system well and give an overall IP3 of 34.8 dBm.

An attenuator of 13 dB would then produce the right noise figure for 40 m with an IP3 of 47.8 dBm.

Maximum signal

The maximum signal input must be considered as an A/D converter has a hard limit. The front end band pass filter on 40 m will give virtually zero attenuation to the nearby broadcast bands. This means that these large signals (s9 +60dB) will be present in the receiver. We do not have a crystal filter removing them early on.

With 1.5 dBm maximum at the A/D and 15.2 dB of gain in front the maximum signal at the Rx input is ?13.7dBm or S9+59.3 dB. (Without the extra attenuator) The attenuator will still give some headroom with several of these signals adding. The final system appears well match to the real world.

Summary

Noise figure 10.3 dB 23 dB with attenuator
IP3 34.8 dBm 47.8 with attenuator
Max signal s9+62 dB s9 +75 with attenuator

Preamplifier requirements:

Gain 15 dB
Noise figure 3 dB
IP3in 35 dB (Output IP3 50 dB)

With no amp:

Noise figure 23.4 dB
IP3 46.8 dBm
Max signal s9+77 dB

It is actually better to use an plus attenuator. It gives a better IP3 than with no amplifier as the attenuator is placed before the filter and switching which each contribute there own limitation to the IP3 in the spreadsheet although these are estimated figures. The amplifier also produces a useful interface to the A/D.

18th June 2006. The image above is of the LT2208 connected via a Xylo FPGA board over USB 2 to PowerSDR. The input signal level is 0dBm and we have about 100dB of dynamic range. Thanks to Bill KD5TFD for modifying PowerSDR to take the 16 bit data from the LT2208.

The Verilog code in the Xylo FPGA implements a fixed NCO on 25.00MHz and multiplies the 16 bits of data from the LT2208 alternately buy 1 or or -1. This is followed by a CIC filter that decimates the data by 2048. Since the LT2208 is clocked at 100MHz this results in a data rate of approximately 48.8kHz.

Next we will implement a CORDIC based NCO to provide tunable frequency control plus a half band filter to follow the CIC. Assuming this will all fit in the Xylo FPGA! If not we will have to wait for the OZY board to do further testing.

The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.0 software

Phil...VK6APH

PENELOPE

2007-08-16T00:41:28Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==
15th August 2007 - Alpha 2 kits all shipped today.

11th August 2007 - Alpha 2 kits are ready to ship except for three (3) parts due on the 14th. Added photos of bare boards (below).

2nd August 2007 - Alpha 2 files uploaded. Alpha 2 parts have been ordered and kits are expected to ship out by the 15th of this month. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=639
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=638
:Costed BOM : had errors, deleted

12th May 2007 - Updated Verilog block diagram.

7th May 2007 - Added ALC code, updated Verilog block diagram.

3rd May 2007 - Alpha PCB working, V2 PCB presently being layed out, block diagram updated to reflect latest changes.

19th April 2007 - Alpha 1 kits sent to Penelope testers!

14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : see August 2nd, above.
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : see August 2nd, above. 
:Initial PCB Layout posted here: see August 2nd, above.
:Initial BOM posted here: see August 2nd, above. 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v10.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 2 Board

[[Image:Penny2frontbare.gif]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cut trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

23rd April 2007: 
:U31 pin 3 not connected to 3V3. Jumper to U36.
:L27 doesn't pick up 3V3. Jumper to U36.
:U11 pin 2 not grounded. Jumper to C41 or C50.
:PCB silkscreen doesn't show pin 1 on Hittite switches. U9 - lower left. U12 - upper right. Right hand bank of filter switches: lower right. Left hand bank of filter switches: upper left.

PENELOPE

2007-08-11T22:14:51Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==
11th August 2007 - Alpha 2 kits are ready to ship except for three (3) parts due on the 14th. Added photos of bare boards (below).

2nd August 2007 - Alpha 2 files uploaded. Alpha 2 parts have been ordered and kits are expected to ship out by the 15th of this month. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=639
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=638
:Costed BOM : had errors, deleted

12th May 2007 - Updated Verilog block diagram.

7th May 2007 - Added ALC code, updated Verilog block diagram.

3rd May 2007 - Alpha PCB working, V2 PCB presently being layed out, block diagram updated to reflect latest changes.

19th April 2007 - Alpha 1 kits sent to Penelope testers!

14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : see August 2nd, above.
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : see August 2nd, above. 
:Initial PCB Layout posted here: see August 2nd, above.
:Initial BOM posted here: see August 2nd, above. 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v10.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 2 Board

[[Image:Penny2frontbare.gif]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cut trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

23rd April 2007: 
:U31 pin 3 not connected to 3V3. Jumper to U36.
:L27 doesn't pick up 3V3. Jumper to U36.
:U11 pin 2 not grounded. Jumper to C41 or C50.
:PCB silkscreen doesn't show pin 1 on Hittite switches. U9 - lower left. U12 - upper right. Right hand bank of filter switches: lower right. Left hand bank of filter switches: upper left.

File:Penny2frontbare.gif

2007-08-11T22:12:56Z

KK7P:

PENELOPE

2007-08-03T02:26:28Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==

2nd August 2007 - Alpha 2 files uploaded. ALpha 2 parts have been ordered and kits are expected to ship out by the 15th of this month. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=639
:Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=638
:Costed BOM : http://www.hamsdr.com/personaldirectory.aspx?id=637

12th May 2007 - Updated Verilog block diagram.

7th May 2007 - Added ALC code, updated Verilog block diagram.

3rd May 2007 - Alpha PCB working, V2 PCB presently being layed out, block diagram updated to reflect latest changes.

19th April 2007 - Alpha 1 kits sent to Penelope testers!

14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : see August 2nd, above.
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : see August 2nd, above. 
:Initial PCB Layout posted here: see August 2nd, above.
:Initial BOM posted here: see August 2nd, above. 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v10.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 1 Boards

[[Image:pennybare.gif]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cut trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

23rd April 2007: 
:U31 pin 3 not connected to 3V3. Jumper to U36.
:L27 doesn't pick up 3V3. Jumper to U36.
:U11 pin 2 not grounded. Jumper to C41 or C50.
:PCB silkscreen doesn't show pin 1 on Hittite switches. U9 - lower left. U12 - upper right. Right hand bank of filter switches: lower right. Left hand bank of filter switches: upper left.

SASQUATCH

2007-07-23T17:40:24Z

KK7P:

==SASQUATCH - DSP back-end==

The Sasquatch board is a proposed DSP back-end intended for use by constructors who would like to operate the HPSDR stand-alone rather than attached to a PC.

Sasquatch could have the logic needed to implement a highly efficient VHF transmitter using envelope elimination and restoration techniques.

Required Reading for EER/HELAPS:

HELAPS article from AMSAT Eagle Pedia http://www.amsat.org/amsat-new/eagle/EaglePedia/index.php/Image:HELAPS_D_considerations.pdf

2401 MHz HELAPS transmitter block diagram http://www.amsat.org/amsat-new/eagle/EaglePedia/index.php/Image:HELAPS_D_preliminary_block_diagram_-_N2UO.pdf

RF Power Amplifiers, Mihai Albulet, Noble Publishing, ISBN 1-884932-12-6 http://hpsdr.org/wiki/index.php?title=Special:Booksources&isbn=1884932126

RF Power Amplifiers for Wireless Communications, Steve Cripps, Artech House, ISBN 0-89006-989-1
http://hpsdr.org/wiki/index.php?title=Special:Booksources&isbn=0890069891

Advanced Techniques in RF Power Amplifier Design, Steve Cripps, Artech House, ISBN 1-58053-282-9
http://hpsdr.org/wiki/index.php?title=Special:Booksources&isbn=1580532829

Watch this space...

Janus

2007-05-16T00:27:07Z

KK7P:

==JANUS - ADC/DAC Board==

The project leaders for the board are Bill Tracey, KD5TFD and Phil Harman, VK6APH. Lyle Johnson, KK7P did the PCB layout.

== Introduction ==

The Janus module is a very high performance, dual, full duplex, A/D and D/A converter board. The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.

Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.

The Janus board needs to be paired with an Ozy board in order to provide a high performance sound card replacement. This combination enables a single USB connection to provide all audio connections to the SDR hardware as well as acting as a parallel port replacement for the Flex-Radio SDR1000 (TM).

The consumer demand for high quality PC sound cards has resulted in the availability of a number of very high performance, and low cost, A/D and D/A converter chips that are ideal candidates for this project.

A block diagram of Janus is shown below.

[[Image:Janus.jpg]]

Block diagram of the Janus Verilog code

[[Image:Janus_Verilog.jpg]]

== Current Status ==

May 15 2007 - Uploaded AB1DO's Janus+Ozy+PowerSDR Document at http://www.hamsdr.com/personaldirectory.aspx?id=564

February 14 2007 - Production schematic files now at http://www.hamsdr.com/personaldirectory.aspx?id=501 and production BOM file now at http://www.hamsdr.com/personaldirectory.aspx?id=502. Only change from previous version is change of 2K resistors to 10K resistors for PWM input filter. KK7P

Feburary 12 2007 - Design released for production. VK6APH & KK7P.

February 01 2007 - Production PCB files now at http://www.hamsdr.com/personaldirectory.aspx?id=485 Minor changes to improve manufacurability. KK7P

January 29 2007 - uploaded 2006 ARRL/TAPR DCC paper on Janus: [[Media:Janus-DCC-2006-paper.pdf]]

December 23 - Updated (production!) PCB files now at (link deleted, see Feb 01 2007 ). Includes solder paste layer, minor tweaks to silkscreen layer and better separation of vias from SMT pads to facilitate automated assembly (and helpful for those of you who use toaster ovens to solder your boards!). KK7P

December 10 - Janus V2 tested with Ozy V2, all appears to work OK. VK6APH

November 21 - Initial check out of Alpha 2 board indicates all functions work OK. VK6APH

November 18 - Photo of Janus updated with Alpha 2 board. All kits are confirmed in the hands of the test team. KK7P

November 10 - PCBs arived early (thanks, FedEx!) and Alpha 2 kits were shipped today, Nov 10th. KK7P

November 09 - Alpha 2 PC boards were shipped yesterday, due to arrive Monday 13th. Alpha 2 test kits are ready to ship upon arrival of PC boards. Updated PCB files are now on hamsdr and pointed to by the corrected link below (status dated October 1st). KK7P

October 29 - Alpha board testing is complete!!! Thankyou to Bill, Bob and Rick. Alpha 2 PC boards were ordered today, with expected delivery early next week.

October 20 - Uploaded some screen shots comparing the pricey LT1128CS8 op amps compared to the more value priced NE5534ADR op amps Lyle (KK7P) suggested. Details are on [[OpAmp Bakeoff]]

October 1st - Janus Alpha 2 prototyping is underway. Parts have been ordered for six (6) boards. The changes outlined in the "Janus Alpha Revisions" (below) have been incorporated. The changes have all been tested by hacks on one or more of the original Janus boards. There is a small but significant test yet to be done, after which we will get the new PCB fabricated (assuming the remaining test is successful, of course).

See (link deleted, see Feb 14 2007 ) for the latest schematic (rev XC9).

See (link deleted, see Feb 14 2007 ) for the latest Bill of Materials(rev XC9).

August 15th - Janus has been successfully interfaced to the Ozy board. Currently preparing for Beta version prior to production.

July 14 2006 - All the functions have been tested successfully! The sampling speed (48/96/192k) can be changed from PowerSDR now. Minor changes to the circuit and PCB are being made ready for the production version. The main clock at 12.288MHz has been changed to a VCXO so it can be phase locked to the Mercury reference.

July 13 2006 - See (link deleted, see Feb 14 2007 ) for provisional Janus Beta schematic.

July 08 2006 - See [[JanusAlphaRevisions]] for some notes on revisions needed for the production Janus board.

Update June 21 - All parts are in hand or on the way to alpha builders, and the bring up begins. More info on the bring up of the Apha Janus @ [[JanusBringup]] --kd5tfd.

Update June 07 - Alpha PCBs arrived today! - KK7P

Update 26 May 2006

The results of the ADC bake-off are in and the AK5394A is the clear winner for our particular application due to its flat noise floor at 192kps.

The measured figures of the prototype Janus using the AK5394A are:

Noise Floor = -160dBm (in an 11Hz FFT bandwidth) Dynamic Range = 120dB ENOB = 20 bits

We are now at the final review stages of the Janus circuit and expect to be moving to prototype PCB manufacture very shortly.

The Verilog code for the Xylo board has been changed to support the AK5394A ADC in I2S Slave mode. In addition, the ADC can be switched between 192/96/48kps under control of PowerSDR. The clocking for the TLV320 has been altered so that its ADC and DAC always run at 48kHz. The TLV320 code has also been altered to enable it to run in I2S mode. The clocks for the ADC and DAC are now obtained by dividing down the 24.576MHz rather than running the AK5394A in Master mode.

Bill, KD5TFD, has modified PowerSDR so that it can accept ADC data from the AK53954A at 192/96/48kps and send received DAC data back to the TLV320 at 48kHz. He has also modified the code to up-sample the 48kHz microphone/line-in data from the TLV320 to 192/96kps.

Bill's modifications to the PowerSDR sofware provides 3 A/D inputs ( I, Q, and line/microphone) and 4 outputs (left/right receiver audio and I/Q audio for the exciter). These are both full duplex so VOX etc. operation works just fine. He has also added PTT and CW inputs to the FPGA and these appear to provide very low latency inputs to PowerSDR.

The document that describes the protocol used over the USB to/from the PC can be found below in the documentation section for JANUS.

Phil, VK6APH

The PCB for the Janus board was laid out by Lyle, KK7P. The latest version of the Alpha schematic may be found at (link deleted, see Feb 14 2007 ) and the PCB layout is at (link deleted, see Feb 01 2007 ) for viewing or download.

Note that the PCB follows Phil Covington's 120mm x 100mm suggestion. Minor edits have been made to the schematic to incorporate the latest changes from Phil Harman.

You will note that copyrights have been asserted to both the schematic and the PCB layout. This is to protect the content while we figure out how to make this open source. Some of us have had the unpleasant experience in the past of a third party taking our work, claiming it as their own, and then demanding compensation! Note that there is no guarantee that this design does not infringe on someone's patents, designs or claims; use it at your own risk.

A photograph of the first assembled Alpha 2 board (11/18) is here: [[Image:Janusalpha2.gif]]

The selection of A/D converter for microphone and line inputs and D/A converters for audio out and I/Q signals for the transmitter was somewhat simpler. It was hard to go past the TI TLV320AIC23B. This remarkable chip contains a microphone amplifier, with bias feed for an electret microphone, stereo line in and out, stereo 16-bit A/D and D/A converters together with 35mW stereo headphone amplifier. The price for this chip is $7 (US) in single quantities. We have a lot to thank MP3 players for!

== Circuit Description ==

This description applies to the Rev XC11 schematic, released February 14, 2007.

'''Sheet 1 - BUS INTERFACE and CPLD'''

The 96-pin DIN connector which plugs into the ATLAS backplane is in the upper left of the page, labeled P1A..P1C.

U11 is an Altera EPM240 CPLD. [http://www.altera.com/products/devices/cpld/max2/mx2-index.jsp] This is actually a small, SRAM-based FPGA similar to the Cyclone series. It has an on-chip Flash configuration memory. U11 is used to map the ATLAS buses to the ADC, CODEC and PWM on Janus. It also provides clocks to the ADC and CODEC, derived from XO1, or accepts an external clock if multiple Janus boards are installed. Three unused pins on the device are used for a test point (TP3) and to drive a pair of LEDs (LED4, LED5) under program/CPLD control.

XO1 is a voltage controlled crystal oscillator. A digital phase locked loop is implemented in the CPLD, and the resistors and capacitors associate with the TUNE line going to XO1 pin 1 are used to filter the pulses from the CPLD to a DC voltage. Initial experiments show a lock time on the order of 15 seconds. The intent is to slave this crystal oscillator a very stable reference (see the Gibraltar project, for example), so a slow response with very low noise is prefered to a fast response with noisy sidebands.

P2 allows local configuration of U11 by a standard Altera-compatible JTAG programmer. U11 may also be programmed over the ATLAS bus by another device, such as Ozymandias. For the latter, JP12 must be placed if Janus is the last card from the master. There must be no empty slots beween Ozymandias and Janus for this to work, and Ozymandias must be "upstream" from Janus. If all slots are filled, then the "upstream" requirement is no longer in force.

An I2C interface is provided to configure the CODEC (on sheet 3) as well as to the CPLD if an I2C function is programmed into it. JP10 and JP11 may be placed to directly conenct the CODEC to the ATLAS I2C bus pins. R34 and R37 are local pull ups to enable to I2C open-collector logic.

U13 [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4272] provides a unique 64-bit serial number as well as 128 bytes of EEPROM memory on a Dallas 1-wire bus. This is to support remote identification and configuration of Janus, for example by Ozymandias.

RP1-6 provide a statis bleed-off path to protect Janus' circuitry from damage when the board is inserted into a backplane, and from undriven inputs.

'''Sheet 2 - ADC'''

U7 is the AKM AK5394A ADC chip. [http://www.asahi-kasei.co.jp/akm/en/product/ak5394a/ak5394a.html] This is a 2 channel, 24-bit component with excellent specifications and capable of operation beyond 200 kilosamples/second. Significant bypassing is required on various pins of this device.

U2 provides bias voltage for the input buffer amplifiers, and R10 is selected to match the buffer amplifier offset to the ADC inputs.

There are two channels of input amplifer, the left is discussed, the right is similar.

Assuming a balanced input applied to J2 (external cable) or P3 (adjacent board), one side is coupled through FL3 to U4. FL3 helps to isolate noise on the input, perhaps stray RF. R22 introduces DC bias, C26 couples the audio signal. U4 buffers the signal, with R19, R21 and C2 arranged to maximize dynamic range and minimize noise. The other side of the balanced input signal is similarly buffered by U6.

This input configuration was chosen for high input impedance to minimize loading on a QSD-style detector that might drive Janus. This circuit is not compatible with "professional audio" signal levels or impedance.

U6/U4 outputs are bypassed by C22, working in conjunction with R19/R21/R25/R26 to provide rolloff for the sigma-delta ADC convertor within U7.

If an unbalanced signal is required, then jumpers JP4 and JP6 are placed. The input signal is applied to U4, and the output from U4 is coupled to the inverting input of U6 through R23/JP6 so that U6 provides inverting, unity gain. The non-inverting input of U6 is shunted by JP4.

If a higher level signal input tolerance is required, JP5 is removed and R17 reduces the input ampltitude, working against the nominal input impedance of the buffer amplifier.

'''Sheet 3 - CODEC and PWM'''

U9 is a TI TLV320AIC23B [http://focus.ti.com/docs/prod/folders/print/tlv320aic23b.html] 2-channel CODEC (COder/DECoder) which has ADC and DAC functions. It is fully configured by the FPGA. Signals are bypassed for RF and AC coupled to the analog inputs or from the analog outputs of U9. U9 is intended to provide "baseband" audio I/O for the HPSDR. Note that no speaker amplifier is provided on Janus.

Just as 8-pin microphone connectors adhere to no standards in Amateur radio, simple 3.5mm microphone connectors are also "standards free." JP7..JP9 allow configuration of the microphone connector. JP7 may be placed to apply DC bias to the tip or ring of the mic connector, or left off if no bias is required (e.g., a dynamic mic). JP8 selects the tip or ring for PTT, or may be left off if the mic has no PTT function. JP9 selects the tip or ring for mic audio. This jumper must be placed!

The PTT signal is pulled high by R35, and the PTT assertion (pulled to ground) is coupled by D1. R33 and C58 provide further decoupling of the PTT input.

U14 provides integration and buffering of the PWM signals from Ozy or some other source on the ATLAS backplane. These outputs are intended to drive a QSE mixer for transmission.

'''Sheet 4 - Power Supply'''

U12 and associated bypass capacitors supply +3V3. This is the primary digital power supply, as well as the CODEC analog supply.

U8 is the +5V regulator, which is used by the AKM AK5394A ADC on sheet 2.

U5 supplies +10V, used in the ADC, PWM and CODEC analog buffer amplifiers.

U10 provides -5V, used by the ADC analog buffer amplifiers.

Four (4) LEDs are visual indicators that the various supplies are working.

J8 is an optional terminal strip connector to simplify powering Janus if the Atlas backplane is not present.

'''Preliminary Parts List'''

The parts list for Rev XC9 of Janus in Excel format is here: (link deleted, see Feb 14 2007 )

* The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.1 software

== Documentation ==

There are two parts of the written documentation in planning. Part #1 documents the schematic as well as the USB protocol for JANUS. Part #2 shows the board assembly as well as additional information.

Part #1 is available at: http://www.needles.de/HPSDR/JANUS_1_DocuUSLet.pdf

Part #2 will be available soon.

Janus

2007-05-16T00:24:14Z

KK7P:

==JANUS - ADC/DAC Board==

The project leaders for the board are Bill Tracey, KD5TFD and Phil Harman, VK6APH. Lyle Johnson, KK7P did the PCB layout.

== Introduction ==

The Janus module is a very high performance, dual, full duplex, A/D and D/A converter board. The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.

Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.

The Janus board needs to be paired with an Ozy board in order to provide a high performance sound card replacement. This combination enables a single USB connection to provide all audio connections to the SDR hardware as well as acting as a parallel port replacement for the Flex-Radio SDR1000 (TM).

The consumer demand for high quality PC sound cards has resulted in the availability of a number of very high performance, and low cost, A/D and D/A converter chips that are ideal candidates for this project.

A block diagram of Janus is shown below.

[[Image:Janus.jpg]]

Block diagram of the Janus Verilog code

[[Image:Janus_Verilog.jpg]]

== Current Status ==

May 15 2007 - Uploaded AB1DO's Jnaus+Ozy+PowerSDR Document at http://www.hamsdr.com/personaldirectory.aspx?id=564

February 14 2007 - Production schematic files now at http://www.hamsdr.com/personaldirectory.aspx?id=501 and production BOM file now at http://www.hamsdr.com/personaldirectory.aspx?id=502. Only change from previous version is change of 2K resistors to 10K resistors for PWM input filter. KK7P

Feburary 12 2007 - Design released for production. VK6APH & KK7P.

February 01 2007 - Production PCB files now at http://www.hamsdr.com/personaldirectory.aspx?id=485 Minor changes to improve manufacurability. KK7P

January 29 2007 - uploaded 2006 ARRL/TAPR DCC paper on Janus: [[Media:Janus-DCC-2006-paper.pdf]]

December 23 - Updated (production!) PCB files now at (link deleted, see Feb 01 2007 ). Includes solder paste layer, minor tweaks to silkscreen layer and better separation of vias from SMT pads to facilitate automated assembly (and helpful for those of you who use toaster ovens to solder your boards!). KK7P

December 10 - Janus V2 tested with Ozy V2, all appears to work OK. VK6APH

November 21 - Initial check out of Alpha 2 board indicates all functions work OK. VK6APH

November 18 - Photo of Janus updated with Alpha 2 board. All kits are confirmed in the hands of the test team. KK7P

November 10 - PCBs arived early (thanks, FedEx!) and Alpha 2 kits were shipped today, Nov 10th. KK7P

November 09 - Alpha 2 PC boards were shipped yesterday, due to arrive Monday 13th. Alpha 2 test kits are ready to ship upon arrival of PC boards. Updated PCB files are now on hamsdr and pointed to by the corrected link below (status dated October 1st). KK7P

October 29 - Alpha board testing is complete!!! Thankyou to Bill, Bob and Rick. Alpha 2 PC boards were ordered today, with expected delivery early next week.

October 20 - Uploaded some screen shots comparing the pricey LT1128CS8 op amps compared to the more value priced NE5534ADR op amps Lyle (KK7P) suggested. Details are on [[OpAmp Bakeoff]]

October 1st - Janus Alpha 2 prototyping is underway. Parts have been ordered for six (6) boards. The changes outlined in the "Janus Alpha Revisions" (below) have been incorporated. The changes have all been tested by hacks on one or more of the original Janus boards. There is a small but significant test yet to be done, after which we will get the new PCB fabricated (assuming the remaining test is successful, of course).

See (link deleted, see Feb 14 2007 ) for the latest schematic (rev XC9).

See (link deleted, see Feb 14 2007 ) for the latest Bill of Materials(rev XC9).

August 15th - Janus has been successfully interfaced to the Ozy board. Currently preparing for Beta version prior to production.

July 14 2006 - All the functions have been tested successfully! The sampling speed (48/96/192k) can be changed from PowerSDR now. Minor changes to the circuit and PCB are being made ready for the production version. The main clock at 12.288MHz has been changed to a VCXO so it can be phase locked to the Mercury reference.

July 13 2006 - See (link deleted, see Feb 14 2007 ) for provisional Janus Beta schematic.

July 08 2006 - See [[JanusAlphaRevisions]] for some notes on revisions needed for the production Janus board.

Update June 21 - All parts are in hand or on the way to alpha builders, and the bring up begins. More info on the bring up of the Apha Janus @ [[JanusBringup]] --kd5tfd.

Update June 07 - Alpha PCBs arrived today! - KK7P

Update 26 May 2006

The results of the ADC bake-off are in and the AK5394A is the clear winner for our particular application due to its flat noise floor at 192kps.

The measured figures of the prototype Janus using the AK5394A are:

Noise Floor = -160dBm (in an 11Hz FFT bandwidth) Dynamic Range = 120dB ENOB = 20 bits

We are now at the final review stages of the Janus circuit and expect to be moving to prototype PCB manufacture very shortly.

The Verilog code for the Xylo board has been changed to support the AK5394A ADC in I2S Slave mode. In addition, the ADC can be switched between 192/96/48kps under control of PowerSDR. The clocking for the TLV320 has been altered so that its ADC and DAC always run at 48kHz. The TLV320 code has also been altered to enable it to run in I2S mode. The clocks for the ADC and DAC are now obtained by dividing down the 24.576MHz rather than running the AK5394A in Master mode.

Bill, KD5TFD, has modified PowerSDR so that it can accept ADC data from the AK53954A at 192/96/48kps and send received DAC data back to the TLV320 at 48kHz. He has also modified the code to up-sample the 48kHz microphone/line-in data from the TLV320 to 192/96kps.

Bill's modifications to the PowerSDR sofware provides 3 A/D inputs ( I, Q, and line/microphone) and 4 outputs (left/right receiver audio and I/Q audio for the exciter). These are both full duplex so VOX etc. operation works just fine. He has also added PTT and CW inputs to the FPGA and these appear to provide very low latency inputs to PowerSDR.

The document that describes the protocol used over the USB to/from the PC can be found below in the documentation section for JANUS.

Phil, VK6APH

The PCB for the Janus board was laid out by Lyle, KK7P. The latest version of the Alpha schematic may be found at (link deleted, see Feb 14 2007 ) and the PCB layout is at (link deleted, see Feb 01 2007 ) for viewing or download.

Note that the PCB follows Phil Covington's 120mm x 100mm suggestion. Minor edits have been made to the schematic to incorporate the latest changes from Phil Harman.

You will note that copyrights have been asserted to both the schematic and the PCB layout. This is to protect the content while we figure out how to make this open source. Some of us have had the unpleasant experience in the past of a third party taking our work, claiming it as their own, and then demanding compensation! Note that there is no guarantee that this design does not infringe on someone's patents, designs or claims; use it at your own risk.

A photograph of the first assembled Alpha 2 board (11/18) is here: [[Image:Janusalpha2.gif]]

The selection of A/D converter for microphone and line inputs and D/A converters for audio out and I/Q signals for the transmitter was somewhat simpler. It was hard to go past the TI TLV320AIC23B. This remarkable chip contains a microphone amplifier, with bias feed for an electret microphone, stereo line in and out, stereo 16-bit A/D and D/A converters together with 35mW stereo headphone amplifier. The price for this chip is $7 (US) in single quantities. We have a lot to thank MP3 players for!

== Circuit Description ==

This description applies to the Rev XC11 schematic, released February 14, 2007.

'''Sheet 1 - BUS INTERFACE and CPLD'''

The 96-pin DIN connector which plugs into the ATLAS backplane is in the upper left of the page, labeled P1A..P1C.

U11 is an Altera EPM240 CPLD. [http://www.altera.com/products/devices/cpld/max2/mx2-index.jsp] This is actually a small, SRAM-based FPGA similar to the Cyclone series. It has an on-chip Flash configuration memory. U11 is used to map the ATLAS buses to the ADC, CODEC and PWM on Janus. It also provides clocks to the ADC and CODEC, derived from XO1, or accepts an external clock if multiple Janus boards are installed. Three unused pins on the device are used for a test point (TP3) and to drive a pair of LEDs (LED4, LED5) under program/CPLD control.

XO1 is a voltage controlled crystal oscillator. A digital phase locked loop is implemented in the CPLD, and the resistors and capacitors associate with the TUNE line going to XO1 pin 1 are used to filter the pulses from the CPLD to a DC voltage. Initial experiments show a lock time on the order of 15 seconds. The intent is to slave this crystal oscillator a very stable reference (see the Gibraltar project, for example), so a slow response with very low noise is prefered to a fast response with noisy sidebands.

P2 allows local configuration of U11 by a standard Altera-compatible JTAG programmer. U11 may also be programmed over the ATLAS bus by another device, such as Ozymandias. For the latter, JP12 must be placed if Janus is the last card from the master. There must be no empty slots beween Ozymandias and Janus for this to work, and Ozymandias must be "upstream" from Janus. If all slots are filled, then the "upstream" requirement is no longer in force.

An I2C interface is provided to configure the CODEC (on sheet 3) as well as to the CPLD if an I2C function is programmed into it. JP10 and JP11 may be placed to directly conenct the CODEC to the ATLAS I2C bus pins. R34 and R37 are local pull ups to enable to I2C open-collector logic.

U13 [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4272] provides a unique 64-bit serial number as well as 128 bytes of EEPROM memory on a Dallas 1-wire bus. This is to support remote identification and configuration of Janus, for example by Ozymandias.

RP1-6 provide a statis bleed-off path to protect Janus' circuitry from damage when the board is inserted into a backplane, and from undriven inputs.

'''Sheet 2 - ADC'''

U7 is the AKM AK5394A ADC chip. [http://www.asahi-kasei.co.jp/akm/en/product/ak5394a/ak5394a.html] This is a 2 channel, 24-bit component with excellent specifications and capable of operation beyond 200 kilosamples/second. Significant bypassing is required on various pins of this device.

U2 provides bias voltage for the input buffer amplifiers, and R10 is selected to match the buffer amplifier offset to the ADC inputs.

There are two channels of input amplifer, the left is discussed, the right is similar.

Assuming a balanced input applied to J2 (external cable) or P3 (adjacent board), one side is coupled through FL3 to U4. FL3 helps to isolate noise on the input, perhaps stray RF. R22 introduces DC bias, C26 couples the audio signal. U4 buffers the signal, with R19, R21 and C2 arranged to maximize dynamic range and minimize noise. The other side of the balanced input signal is similarly buffered by U6.

This input configuration was chosen for high input impedance to minimize loading on a QSD-style detector that might drive Janus. This circuit is not compatible with "professional audio" signal levels or impedance.

U6/U4 outputs are bypassed by C22, working in conjunction with R19/R21/R25/R26 to provide rolloff for the sigma-delta ADC convertor within U7.

If an unbalanced signal is required, then jumpers JP4 and JP6 are placed. The input signal is applied to U4, and the output from U4 is coupled to the inverting input of U6 through R23/JP6 so that U6 provides inverting, unity gain. The non-inverting input of U6 is shunted by JP4.

If a higher level signal input tolerance is required, JP5 is removed and R17 reduces the input ampltitude, working against the nominal input impedance of the buffer amplifier.

'''Sheet 3 - CODEC and PWM'''

U9 is a TI TLV320AIC23B [http://focus.ti.com/docs/prod/folders/print/tlv320aic23b.html] 2-channel CODEC (COder/DECoder) which has ADC and DAC functions. It is fully configured by the FPGA. Signals are bypassed for RF and AC coupled to the analog inputs or from the analog outputs of U9. U9 is intended to provide "baseband" audio I/O for the HPSDR. Note that no speaker amplifier is provided on Janus.

Just as 8-pin microphone connectors adhere to no standards in Amateur radio, simple 3.5mm microphone connectors are also "standards free." JP7..JP9 allow configuration of the microphone connector. JP7 may be placed to apply DC bias to the tip or ring of the mic connector, or left off if no bias is required (e.g., a dynamic mic). JP8 selects the tip or ring for PTT, or may be left off if the mic has no PTT function. JP9 selects the tip or ring for mic audio. This jumper must be placed!

The PTT signal is pulled high by R35, and the PTT assertion (pulled to ground) is coupled by D1. R33 and C58 provide further decoupling of the PTT input.

U14 provides integration and buffering of the PWM signals from Ozy or some other source on the ATLAS backplane. These outputs are intended to drive a QSE mixer for transmission.

'''Sheet 4 - Power Supply'''

U12 and associated bypass capacitors supply +3V3. This is the primary digital power supply, as well as the CODEC analog supply.

U8 is the +5V regulator, which is used by the AKM AK5394A ADC on sheet 2.

U5 supplies +10V, used in the ADC, PWM and CODEC analog buffer amplifiers.

U10 provides -5V, used by the ADC analog buffer amplifiers.

Four (4) LEDs are visual indicators that the various supplies are working.

J8 is an optional terminal strip connector to simplify powering Janus if the Atlas backplane is not present.

'''Preliminary Parts List'''

The parts list for Rev XC9 of Janus in Excel format is here: (link deleted, see Feb 14 2007 )

* The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.1 software

== Documentation ==

There are two parts of the written documentation in planning. Part #1 documents the schematic as well as the USB protocol for JANUS. Part #2 shows the board assembly as well as additional information.

Part #1 is available at: http://www.needles.de/HPSDR/JANUS_1_DocuUSLet.pdf

Part #2 will be available soon.

PENELOPE

2007-04-24T04:24:20Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==
19th April 2007 - Alpha 1 kits sent to Penelope testers!

14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=549
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : http://www.hamsdr.com/personaldirectory.aspx?id=534 
:Initial PCB Layout posted here: (replaced 29 Mar 2007)
:Initial BOM posted here: http://www.hamsdr.com/personaldirectory.aspx?id=536 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Solid state antenna changeover relay for fast QSK.
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v9.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 1 Boards

[[Image:pennybare.gif]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cut trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

23rd April 2007: 
:U31 pin 3 not connected to 3V3. Jumper to U36.
:L27 doesn't pick up 3V3. Jumper to U36.
:U11 pin 2 not grounded. Jumper to C41 or C50.
:PCB silkscreen doesn't show pin 1 on Hittite switches. U9 - lower left. U12 - upper right. Right hand bank of filter switches: lower right. Left hand bank of filter switches: upper left.

PENELOPE

2007-04-19T22:32:11Z

KK7P:

PENELOPE

2007-04-19T22:31:24Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==
19th April 2007 - Alpha1 kits sent to Penelope testers!

14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=549
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : http://www.hamsdr.com/personaldirectory.aspx?id=534 
:Initial PCB Layout posted here: (replaced 29 Mar 2007)
:Initial BOM posted here: http://www.hamsdr.com/personaldirectory.aspx?id=536 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Solid state antenna changeover relay for fast QSK.
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v9.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 1 Boards

[[Image:pennybare.gif]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cur trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

PENELOPE

2007-04-14T14:18:39Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==
14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.

13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=549
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : http://www.hamsdr.com/personaldirectory.aspx?id=534 
:Initial PCB Layout posted here: (replaced 29 Mar 2007)
:Initial BOM posted here: http://www.hamsdr.com/personaldirectory.aspx?id=536 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Solid state antenna changeover relay for fast QSK.
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v9.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 1 Boards

[[Image:pennybare.gif]]

''' Alpha 1 Notes: '''

This section will contain notes as we build and learn the mistakes made on Alpha 1.

14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cur trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.

Board Designer's Resources

2007-04-14T00:28:29Z

KK7P:

== Board Designer's Resources ==

This page will provide links to parts used in deployed designs, such as Janus and Ozy. The part information will include manufacturer (such as Texas Instruments) and at least one vendor source (such as Mouser or Digikey). It will also include schematic symbol and PCB footprint libraries for OrCAD and PADS as these are developed.

This page will also provide guidelines for PCB layout (such as necessary clearance for hardware at DIN connector mounting holes), trace minimum widths and apce minimum clearance for keeping PCB costs down, guidelines for PCB footprint creation, and so forth.

The intent is to make it easier for developers to be consistent across teams and projects, and to re-use parts where practical to keep manufacturing costs down for TAPR, which keeps the price down for all of us. -- de KK7P

'''Prototype PCB Suppliers: '''

I have used Protoexpress' "No Touch" service for more than 20 years. Never had a bad board. They are the lowest cost 4-layer prototypes I have found. Many Amateur and some commercial spacecraft in which I have designs are flying these same "No Touch" prototype boards, some since 1993. http://www.protoexpress.com -- de KK7P

Board Designer's Resources

2007-04-14T00:26:08Z

KK7P:

== Board Designer's Resources ==

This page will provide links to parts used in deployed designs, such as Janus and Ozy. The part information will include manufacturer (such as Texas Instruments) and at least one vendor source (such as Mouser or Digikey). It will also include schematic symbol and PCB footprint libraries for OrCAD and PADS as these are developed.

This page will also provide guidelines for PCB layout (such as necessary clearance for hardware at DIN connector mounting holes), trace minimum widths and apce minimum clearance for keeping PCB costs down, guidelines for PCB footprint creation, and so forth.

The intent is to make it easier for developers to be consistent across teams and projects, and to re-use parts where practical to keep manufacturing costs down for TAPR, which keeps the price down for all of us. -- de KK7P

'''Prototype PCB Suppliers: '''

I have used Protoexpress's "No Touch" service for more than 20 years. Never had a bad board. They are the lowest cost 4-layer prototypes I have found. Many Amateur and some commercial spacecraft in which I have designs are flying these same "No Touch" prototype boards, some since 1993. -- de KK7P

PENELOPE

2007-04-13T20:06:34Z

KK7P:

==PENELOPE - Companion Exciter to Mercury==
13th April 2007 - Bare PCBs received! Photo below.

5th April 2007 - Update. 
:PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=549
:TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.

1st April 2007 - Added Verilog block diagram.

30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)

29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)

28th March 2007 - Update. 
:Block diagram updated to reflect prototype PCB layout. 
:Updated Alpha schematic (XA13) for Penelope is here : http://www.hamsdr.com/personaldirectory.aspx?id=534 
:Initial PCB Layout posted here: (replaced 29 Mar 2007)
:Initial BOM posted here: http://www.hamsdr.com/personaldirectory.aspx?id=536 

17th February 2007 - Update. Block diagram updated to reflect latest schematic.

14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)

8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.

7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.

3rd February 2007 - Initial Specification

The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.

Some of the planned features include:

1.8 - 55MHz frequency coverage
0.5W pep output
Low level transverter output
AM, C-AM, FM, CW, PSK etc
RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier
Open drain FET for PTT control of external amplifiers
Seven open collector outputs for Linear, relay etc control,
Solid state antenna changeover relay for fast QSK.
Optional on board microphone ADC or use with a Janus card
Frequency options:
o On board high performance 125MHz crystal oscillator
o External 125MHz source
o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar
o On board 10MHz OCXO/TCXO option
FPGA based DUC enabling future code upgrades
USB interface to PC via Ozy board
I and Q balanced adjustment not required due to digital generation of RF waveform
ADC for ALC or PA linearization etc.
ALC processed in the FPGA to avoid delays associated with PC processing

Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.

Phil... VK6APH

A block diagram is shown below.

[[Image:DUC-v9.jpg]]

Verilog block diagram

[[Image:Penelope_Verilog.jpg]]

Photo of Unpopulated Alpha 1 Boards

[[Image:pennybare.gif]]