Janus - Revision history

OZ1HFT: wiki

2011-04-22T10:54:41Z

wiki

OZ1HFT: more

2011-04-22T10:54:05Z

OZ1HFT: more

2011-04-22T09:55:10Z

OZ1HFT: JANUS moved to Janus

2011-04-21T16:28:07Z

JANUS moved to Janus

OZ1HFT: wiki

2010-01-26T20:31:13Z

wiki

OZ1HFT: wiki, spelling

2010-01-25T20:17:59Z

wiki, spelling

OZ1HFT: catspec

2010-01-25T18:40:42Z

catspec

OZ1HFT: +cat

2010-01-25T17:48:32Z

+cat

VK2NRA: fix link

2009-06-10T00:23:27Z

fix link

VK2NRA: capitalization

2009-05-18T07:19:58Z

capitalization

← Older revision		Revision as of 10:54, 22 April 2011
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−	The '''Janus''' module is a very high performance, dual, full duplex, audio frequency A/D and D/A converter board (soundcard). The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.	+	The '''Janus''' module is a very high performance, dual, full duplex, audio frequency A/D and D/A converter board (soundcard).
		+
		+	The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.

	Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.		Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.

← Older revision		Revision as of 10:54, 22 April 2011
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−	The '''Janus''' module is a very high performance, dual, full duplex, audio frequency A/D and D/A converter board. The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.	+	The '''Janus''' module is a very high performance, dual, full duplex, audio frequency A/D and D/A converter board (soundcard). The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.

	Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.		Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.

← Older revision		Revision as of 09:55, 22 April 2011
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−	The '''Janus''' module is a very high performance, dual, full duplex, A/D and D/A converter board. The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.	+	The '''Janus''' module is a very high performance, dual, full duplex, audio frequency A/D and D/A converter board. The A/D sample rate options are 48, 96 or 192kHz and the D/As are fixed at 48kHz. While the M-Audio Delta 44 has become the de-facto standard for A/D sound cards for use with a SDR, there are a number of advantages to rolling your own. These include having complete control of any software drivers needed to communicate with the A/D chips as well as optimization of sampling rates and bit depths for individual signals. It's also possible to cost effectively develop a board which approaches the performance of professional high end sound cards.

	Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.		Independent testing of the Beta Janus boards has confirmed the very high performance of the completed card.

@@ Line 156: / Line 156: @@
 The parts list for Rev XC9 of Janus in Excel format is here: (link deleted, see Feb 14 2007 )
-    * The Verilog software for the FPGA is being written using the free web version of Altera's Quartus II V6.1 software
+* The Verilog software for the FPGA is being written using the free web version of Altera's Quartus II V6.1 software
 == Documentation ==

@@ Line 21: / Line 21: @@
 February 14 2007 - Production schematic files now at http://www.hamsdr.com/personaldirectory.aspx?id=501 and production BOM file now at http://www.hamsdr.com/personaldirectory.aspx?id=502.  Only change from previous version is change of 2K resistors to 10K resistors for PWM input filter.  KK7P
-Feburary 12 2007 - Design released for production. VK6APH & KK7P.
+February 12 2007 - Design released for production. VK6APH & KK7P.
-February 01 2007 - Production PCB files now at http://www.hamsdr.com/personaldirectory.aspx?id=485 Minor changes to improve manufacurability. KK7P
+February 01 2007 - Production PCB files now at http://www.hamsdr.com/personaldirectory.aspx?id=485 Minor changes to improve manufacturability. KK7P
 January 29 2007 - uploaded 2006 ARRL/TAPR DCC paper on Janus: [[Media:Janus-DCC-2006-paper.pdf]]
@@ Line 35: / Line 35: @@
 November 18 - Photo of Janus updated with Alpha 2 board. All kits are confirmed in the hands of the test team. KK7P
-November 10 - PCBs arived early (thanks, FedEx!) and Alpha 2 kits were shipped today, Nov 10th. KK7P
+November 10 - PCBs arrived early (thanks, FedEx!) and Alpha 2 kits were shipped today, Nov 10th. KK7P
 November 09 - Alpha 2 PC boards were shipped yesterday, due to arrive Monday 13th. Alpha 2 test kits are ready to ship upon arrival of PC boards. Updated PCB files are now on hamsdr and pointed to by the corrected link below (status dated October 1st). KK7P
@@ Line 75: / Line 75: @@
 Bill, KD5TFD, has modified PowerSDR so that it can accept ADC data from the AK53954A at 192/96/48kps and send received DAC data back to the TLV320 at 48kHz. He has also modified the code to up-sample the 48kHz microphone/line-in data from the TLV320 to 192/96kps.
-Bill's modifications to the PowerSDR sofware provides 3 A/D inputs ( I, Q, and line/microphone) and 4 outputs (left/right receiver audio and I/Q audio for the exciter). These are both full duplex so VOX etc. operation works just fine. He has also added PTT and CW inputs to the FPGA and these appear to provide very low latency inputs to PowerSDR.
+Bill's modifications to the PowerSDR software provides 3 A/D inputs ( I, Q, and line/microphone) and 4 outputs (left/right receiver audio and I/Q audio for the exciter). These are both full duplex so VOX etc. operation works just fine. He has also added PTT and CW inputs to the FPGA and these appear to provide very low latency inputs to PowerSDR.
 The document that describes the protocol used over the USB to/from the PC can be found below in the documentation section for JANUS.
@@ Line 100: / Line 100: @@
 U11 is an Altera EPM240 CPLD. [http://www.altera.com/products/devices/cpld/max2/mx2-index.jsp] This is actually a small, SRAM-based FPGA similar to the Cyclone series. It has an on-chip Flash configuration memory. U11 is used to map the ATLAS buses to the ADC, CODEC and PWM on Janus. It also provides clocks to the ADC and CODEC, derived from XO1, or accepts an external clock if multiple Janus boards are installed. Three unused pins on the device are used for a test point (TP3) and to drive a pair of LEDs (LED4, LED5) under program/CPLD control.
-XO1 is a voltage controlled crystal oscillator. A digital phase locked loop is implemented in the CPLD, and the resistors and capacitors associate with the TUNE line going to XO1 pin 1 are used to filter the pulses from the CPLD to a DC voltage. Initial experiments show a lock time on the order of 15 seconds. The intent is to slave this crystal oscillator a very stable reference (see the Gibraltar project, for example), so a slow response with very low noise is prefered to a fast response with noisy sidebands.
+XO1 is a voltage controlled crystal oscillator. A digital phase locked loop is implemented in the CPLD, and the resistors and capacitors associate with the TUNE line going to XO1 pin 1 are used to filter the pulses from the CPLD to a DC voltage. Initial experiments show a lock time on the order of 15 seconds. The intent is to slave this crystal oscillator a very stable reference (see the Gibraltar project, for example), so a slow response with very low noise is preferred to a fast response with noisy sidebands.
-P2 allows local configuration of U11 by a standard Altera-compatible JTAG programmer. U11 may also be programmed over the ATLAS bus by another device, such as Ozymandias. For the latter, JP12 must be placed if Janus is the last card from the master. There must be no empty slots beween Ozymandias and Janus for this to work, and Ozymandias must be "upstream" from Janus. If all slots are filled, then the "upstream" requirement is no longer in force.
+P2 allows local configuration of U11 by a standard Altera-compatible JTAG programmer. U11 may also be programmed over the ATLAS bus by another device, such as Ozymandias. For the latter, JP12 must be placed if Janus is the last card from the master. There must be no empty slots between Ozymandias and Janus for this to work, and Ozymandias must be "upstream" from Janus. If all slots are filled, then the "upstream" requirement is no longer in force.
-An I2C interface is provided to configure the CODEC (on sheet 3) as well as to the CPLD if an I2C function is programmed into it. JP10 and JP11 may be placed to directly conenct the CODEC to the ATLAS I2C bus pins. R34 and R37 are local pull ups to enable to I2C open-collector logic.
+An I2C interface is provided to configure the CODEC (on sheet 3) as well as to the CPLD if an I2C function is programmed into it. JP10 and JP11 may be placed to directly connect the CODEC to the ATLAS I2C bus pins. R34 and R37 are local pull ups to enable to I2C open-collector logic.
 U13 [http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4272] provides a unique 64-bit serial number as well as 128 bytes of EEPROM memory on a Dallas 1-wire bus. This is to support remote identification and configuration of Janus, for example by Ozymandias.
-RP1-6 provide a statis bleed-off path to protect Janus' circuitry from damage when the board is inserted into a backplane, and from undriven inputs.
+RP1-6 provide a statics bleed-off path to protect Janus' circuitry from damage when the board is inserted into a backplane, and from undriven inputs.
 '''Sheet 2 - ADC'''
@@ Line 116: / Line 116: @@
 U2 provides bias voltage for the input buffer amplifiers, and R10 is selected to match the buffer amplifier offset to the ADC inputs.
-There are two channels of input amplifer, the left is discussed, the right is similar.
+There are two channels of input amplifier, the left is discussed, the right is similar.
 Assuming a balanced input applied to J2 (external cable) or P3 (adjacent board), one side is coupled through FL3 to U4. FL3 helps to isolate noise on the input, perhaps stray RF. R22 introduces DC bias, C26 couples the audio signal. U4 buffers the signal, with R19, R21 and C2 arranged to maximize dynamic range and minimize noise. The other side of the balanced input signal is similarly buffered by U6.
@@ Line 122: / Line 122: @@
 This input configuration was chosen for high input impedance to minimize loading on a QSD-style detector that might drive Janus. This circuit is not compatible with "professional audio" signal levels or impedance.
-U6/U4 outputs are bypassed by C22, working in conjunction with R19/R21/R25/R26 to provide rolloff for the sigma-delta ADC convertor within U7.
+U6/U4 outputs are bypassed by C22, working in conjunction with R19/R21/R25/R26 to provide rolloff for the sigma-delta ADC converter within U7.
 If an unbalanced signal is required, then jumpers JP4 and JP6 are placed. The input signal is applied to U4, and the output from U4 is coupled to the inverting input of U6 through R23/JP6 so that U6 provides inverting, unity gain. The non-inverting input of U6 is shunted by JP4.
-If a higher level signal input tolerance is required, JP5 is removed and R17 reduces the input ampltitude, working against the nominal input impedance of the buffer amplifier.
+If a higher level signal input tolerance is required, JP5 is removed and R17 reduces the input amplitude, working against the nominal input impedance of the buffer amplifier.
 '''Sheet 3 - CODEC and PWM'''
@@ Line 156: / Line 156: @@
 The parts list for Rev XC9 of Janus in Excel format is here: (link deleted, see Feb 14 2007 )
-     * The Verilog sofware for the FPGA is being written using the free web version of Altera's Quartus II V6.1 software
+     * The Verilog software for the FPGA is being written using the free web version of Altera's Quartus II V6.1 software
 == Documentation ==
 There are two parts of the written documentation in planning. Part #1 documents the schematic as well as the USB protocol for JANUS. Part #2 shows the board assembly as well as additional information.
+* Part #1 is available at: http://www.needles.de/HPSDR/JANUS_1_DocuUSLet.pdf
-Part #1 is available at: http://www.needles.de/HPSDR/JANUS_1_DocuUSLet.pdf
+* Part #2 will be available soon.
-−
 Part #2 will be available soon.
 [[Category:Janus| ]]

← Older revision	Revision as of 16:28, 21 April 2011
(No difference)

← Older revision		Revision as of 18:40, 25 January 2010
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	Part #2 will be available soon.		Part #2 will be available soon.

−	[[Category:~~Hardware available~~]]	+	[[Category:Janus\| ]]

← Older revision		Revision as of 17:48, 25 January 2010
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	Part #2 will be available soon.		Part #2 will be available soon.
		+
		+	[[Category:Hardware available]]

@@ Line 41: / Line 41: @@
 October 29 - Alpha board testing is complete!!! Thankyou to Bill, Bob and Rick. Alpha 2 PC boards were ordered today, with expected delivery early next week.
-October 20 - Uploaded some screen shots comparing the pricey LT1128CS8 op amps compared to the more value priced NE5534ADR op amps Lyle (KK7P) suggested. Details are on [[OpAmp Bakeoff]]
+October 20 - Uploaded some screen shots comparing the pricey LT1128CS8 op amps compared to the more value priced NE5534ADR op amps Lyle (KK7P) suggested. Details are on [[JANUS OpAmp Bakeoff]]
 October 1st - Janus Alpha 2 prototyping is underway. Parts have been ordered for six (6) boards. The changes outlined in the "Janus Alpha Revisions" (below) have been incorporated. The changes have all been tested by hacks on one or more of the original Janus boards. There is a small but significant test yet to be done, after which we will get the new PCB fabricated (assuming the remaining test is successful, of course).

@@ Line 86: / Line 86: @@
 Note that the PCB follows Phil Covington's 120mm x 100mm suggestion. Minor edits have been made to the schematic to incorporate the latest changes from Phil Harman.
-You will note that copyrights have been asserted to both the schematic and the PCB layout. This is to protect the content while we figure out how to make this open source. Some of us have had the unpleasant experience in the past of a third party taking our work, claiming it as their own, and then demanding compensation! Note that there is no guarantee that this design does not infringe on someone's patents, designs or claims; use it at your own risk. [[Image:Janusalpha2.gif|frame|first assembled Alpha 2 board, Feb 2007]]
+You will note that copyrights have been asserted to both the schematic and the PCB layout. This is to protect the content while we figure out how to make this open source. Some of us have had the unpleasant experience in the past of a third party taking our work, claiming it as their own, and then demanding compensation! Note that there is no guarantee that this design does not infringe on someone's patents, designs or claims; use it at your own risk. [[Image:Janusalpha2.gif|frame|First assembled Alpha 2 board, Feb 2007]]
 The selection of A/D converter for microphone and line inputs and D/A converters for audio out and I/Q signals for the transmitter was somewhat simpler. It was hard to go past the TI TLV320AIC23B. This remarkable chip contains a microphone amplifier, with bias feed for an electret microphone, stereo line in and out, stereo 16-bit A/D and D/A converters together with 35mW stereo headphone amplifier. The price for this chip is $7 (US) in single quantities. We have a lot to thank MP3 players for!