JanusBringup - Revision history

OZ1HFT: spelling

2010-01-25T20:20:58Z

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OZ1HFT: +cat

2010-01-25T18:42:16Z

+cat

WikiSysop: New page: ==Janus Meet Xylo, Xylo meet Janus== All of the parts are in hand, (or in the mail to the builders) and the boards are in hand so it's time to see if this thing works. Inital work will be...

2007-02-14T19:38:07Z

New page: ==Janus Meet Xylo, Xylo meet Janus== All of the parts are in hand, (or in the mail to the builders) and the boards are in hand so it's time to see if this thing works. Inital work will be...

New page

==Janus Meet Xylo, Xylo meet Janus==

All of the parts are in hand, (or in the mail to the builders) and the boards are in hand so it's time to see if this thing works. Inital work will be to check out the Janus board using the Xylo FPGA board. The setup I'll use to do this is shown below

[[Image:Xylojan.jpg]]

This should allow us to get the Janus checked out with the Xylo FPGA we've built the prototypes with and position us well to introduce Janus to Ozy.

Initial plan is to build up the voltage regulator section and check it out first. Next will be to install the clock and the CPLD. Will probably develop a CPLD that puts two different clocks on every other IO pin so I can validate all of the CPLD connections are good before installing the remaining parts. Once the CPLD connections are tested good, the rest of the parts go on, and a new CPLD load is developed to connect the Janus inner connections to the Atlas bus which will be connected to the Xylo shim. For the Xylo prototype I'll be using Row C (YA, YB, and YC series of Atlas signals) of the 96 pin connector to get to the Xylo - do not know if this will be the permanent assignement of the pins once Ozy's ready -- would certainly make debugging easier to swap in and out Ozy or Xylo.

Atlas Connector Pin Definitions

The Atlas connector definitions I'll be using for the Xylo Shim are

- C25 - Atlas YC7 - Xylo 25, FPGA 89 DbgOut
- C24 - Atlas YC6 - Xylo 23, FPGA 88 Right PWM Out
- C23 - Atlas YC5 - Xylo 21, FPGA 86
- C22 - Atlas YC4 - no assignment (Xylo 19 is GND)
- C21 - Atlas YC3 - Xylo 17, FPGA 79, RX_DIN_TLV320
- C20 - Atlas YC2 - Xylo 15, FPGA 78, TX_DOUT_TLV320
- C19 - Atlas YC1 - Xylo 13, FPGA 76, TX_LRCLK_TLV320
- C18 - Atlas YC0 - no assignment (Xylo 11 is 3.3v)
- C17 - Atlas YB7 - Xylo 9, FPGA 66, 24 MHz Clock
- C16 - Atlas YB6 - Xylo 7, FPGA 72, BCLK
- C15 - Atlas YB5 - Xylo 5, FPGA 74 DOUT
- C14 - Atlas YB4 - Xylo 3, FPGA 71, LRCLK
- C13 - Atlas YB3 - Xylo 1, FPGA 70, AD_RESET?
- C12 - Atlas YB2 - Xylo 2, FPGA 69 ALT_CLOCK_OUT (not needed w/ 24.576 osc on Janus)
- - - Xylo 4 (Gnd)
- C11 - Atlas YB1 - Xylo 6, FPGA 73, Dot
- C10 - Atlas YB0 - Xylo 8, FPGA 75, Dash
- - - Xylo 10 (Gnd)
- - - Xylo 12 (3.3v)
- C9 - Atlas YA7 - Xylo 14, FPGA 77, TX_BCLK_TLV320
- - Xylo 16, (Gnd)
- C8 - Atlas YA6 - Xylo 18, FPGA 84, RX_INLRCLK_TLV320
- C7 - Atlas YA5 - Xylo 20, FPGA 85, CounteeClock (clock to be counted against reflock)
- C6 - Atlas YA4 - Xylo 22, FPGA 87, RefClk (1pps or 10khz)
- - Xylo 24 (Gnd)
- C5 - Atlas YA3 - Xylo 26 FPGA 90, Left PWM out
- C4 - Atlas YA2 - no assignment
- C3 - Atlas YA1 - no assignment
- C2 - Atlas YA0 - no assignment
- A20 - Atlas I2CSCK - Xylo I2C clk
- A21 - Atlas I2CSDA - Xylo I2C data
- A1, B1, C1 - + 12v
- A26, B26, C26 - -12v
- A32, B32, C32 - +5v
- A28, B28, C28 - nc
- A30, B30, C30 - nc

Some of these pin defintions may ulitmately not be used - Reflock and counter are not currently implemented in the Xylo verilog code.

'''Test CPLD Image'''

Have done a bit more work and thinking on the test CPLD image. Initial plan was to take the 24.576 MHz clock and divide it down in the CPLD to produce 19 different frequency clocks and feed those to all of the CPLD pins so one could probe the board with a scope and ensure the CPLD was well soldered by looking for the appropriate frequency signal at the various points on the board. An (untested) CPLD iamge that does this is in SVN now.

Chris (AE6VK) mentioned it would be convinient if this could be done with someone with only a voltmeter. Thought about it a bit and thought yes it should be doable by varying the duty cycle of the waveform applied to the pin and using a simple RC network on the voltmeter one should be able to measure what duty cycle waveform was being measured. Went a little overboard and put the whole thing into LTSpice (BTW - fine free program).

The little VOM adapter circut is below:

[[Image:JanusVOMAdapter.PNG]]

With this jig a 66% duty cycle 3MHz waveform will read a touch over 2 volts on the voltmeter and a 33% duty cycle waveform will read a bit over 1 volt. So a CPLD image that puts 0, 1, 2, or 3.3 volts on all the CPLD pins should allow validation of correct CPLD installation.

'''Info on the LTSpice simulation behind this is at CPLDTestVOMSpiceSimulation'''

Xylo Shim is Built (27 June 2006) The Xylo shim is built - with this shim board will be able to connect Xylo cleanly to the Janus to bring it to life. The base is a Velleman prototype board - not really designed for the 96 bin connector, but a little work on the traces with a Dremel tool fixed that up.

Some pictures

[[Image:Xylo-shim-top-1.jpg]]

[[Image:Xylo-shim-top-2.jpg]]

[[Image:Xylo-shim-bottom-1.jpg]]

Last edited by KD5TFD 26 June 2006

← Older revision		Revision as of 18:42, 25 January 2010
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	Last edited by KD5TFD 26 June 2006		Last edited by KD5TFD 26 June 2006
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		+	[[Category:Janus]]

@@ Line 1: / Line 1: @@
 ==Janus Meet Xylo, Xylo meet Janus==
-All of the parts are in hand, (or in the mail to the builders) and the boards are in hand so it's time to see if this thing works. Inital work will be to check out the Janus board using the Xylo FPGA board. The setup I'll use to do this is shown below
+All of the parts are in hand, (or in the mail to the builders) and the boards are in hand so it's time to see if this thing works. Initial work will be to check out the Janus board using the Xylo FPGA board. The setup I'll use to do this is shown below
 [[Image:Xylojan.jpg]]
@@ Line 7: / Line 7: @@
 This should allow us to get the Janus checked out with the Xylo FPGA we've built the prototypes with and position us well to introduce Janus to Ozy.
-Initial plan is to build up the voltage regulator section and check it out first. Next will be to install the clock and the CPLD. Will probably develop a CPLD that puts two different clocks on every other IO pin so I can validate all of the CPLD connections are good before installing the remaining parts. Once the CPLD connections are tested good, the rest of the parts go on, and a new CPLD load is developed to connect the Janus inner connections to the Atlas bus which will be connected to the Xylo shim. For the Xylo prototype I'll be using Row C (YA, YB, and YC series of Atlas signals) of the 96 pin connector to get to the Xylo - do not know if this will be the permanent assignement of the pins once Ozy's ready -- would certainly make debugging easier to swap in and out Ozy or Xylo.
+Initial plan is to build up the voltage regulator section and check it out first. Next will be to install the clock and the CPLD. Will probably develop a CPLD that puts two different clocks on every other IO pin so I can validate all of the CPLD connections are good before installing the remaining parts. Once the CPLD connections are tested good, the rest of the parts go on, and a new CPLD load is developed to connect the Janus inner connections to the Atlas bus which will be connected to the Xylo shim. For the Xylo prototype I'll be using Row C (YA, YB, and YC series of Atlas signals) of the 96 pin connector to get to the Xylo - do not know if this will be the permanent assignment of the pins once Ozy's ready -- would certainly make debugging easier to swap in and out Ozy or Xylo.
 Atlas Connector Pin Definitions
@@ Line 50: / Line 50: @@
   - A30, B30, C30 - nc
-Some of these pin defintions may ulitmately not be used - Reflock and counter are not currently implemented in the Xylo verilog code.
+Some of these pin definitions may ultimately not be used - Reflock and counter are not currently implemented in the Xylo verilog code.
 '''Test CPLD Image'''
-Have done a bit more work and thinking on the test CPLD image. Initial plan was to take the 24.576 MHz clock and divide it down in the CPLD to produce 19 different frequency clocks and feed those to all of the CPLD pins so one could probe the board with a scope and ensure the CPLD was well soldered by looking for the appropriate frequency signal at the various points on the board. An (untested) CPLD iamge that does this is in SVN now.
+Have done a bit more work and thinking on the test CPLD image. Initial plan was to take the 24.576 MHz clock and divide it down in the CPLD to produce 19 different frequency clocks and feed those to all of the CPLD pins so one could probe the board with a scope and ensure the CPLD was well soldered by looking for the appropriate frequency signal at the various points on the board. An (untested) CPLD image that does this is in SVN now.
-Chris (AE6VK) mentioned it would be convinient if this could be done with someone with only a voltmeter. Thought about it a bit and thought yes it should be doable by varying the duty cycle of the waveform applied to the pin and using a simple RC network on the voltmeter one should be able to measure what duty cycle waveform was being measured. Went a little overboard and put the whole thing into LTSpice (BTW - fine free program).
+Chris (AE6VK) mentioned it would be convenient if this could be done with someone with only a voltmeter. Thought about it a bit and thought yes it should be doable by varying the duty cycle of the waveform applied to the pin and using a simple RC network on the voltmeter one should be able to measure what duty cycle waveform was being measured. Went a little overboard and put the whole thing into LTSpice (BTW - fine free program).
-The little VOM adapter circut is below:
+The little VOM adapter circuit is below:
 [[Image:JanusVOMAdapter.PNG]]