OZY - Revision history

KV0S at 23:17, 28 October 2012

2012-10-28T23:17:25Z

KV0S at 02:00, 21 September 2010

2010-09-21T02:00:31Z

KV0S at 01:59, 21 September 2010

2010-09-21T01:59:40Z

OZ1HFT: catspec

2010-01-25T18:49:35Z

catspec

OZ1HFT: + Category:Hardware no longer available

2010-01-25T17:46:56Z

+ Category:Hardware no longer available

VK2NRA: add link for history and move it there

2009-07-25T01:58:57Z

add link for history and move it there

VK2NRA: more correct Wikipedia link?

2009-06-01T08:16:52Z

VK2NRA: frame block diagrams, move up, remove section head

2009-05-31T22:17:52Z

frame block diagrams, move up, remove section head

VK2NRA: remove dead link, frame and reposition picture

2009-05-31T22:02:46Z

remove dead link, frame and reposition picture

VK2NRA at 09:17, 5 May 2009

2009-05-05T09:17:06Z

@@ Line 16: / Line 16: @@
 Whilst specifically designed to support the various HPSDR modules the OZY board makes an excellent general purpose FPGA development system. The source code to both the FX2 and FPGA software is available under GPL and the board is very cost competitive compared with other FPGA development systems.
-The latest schematic, PCB and BOM of the OZY board can be found at: http://openhpsdr.org/support.html
+The latest schematic, PCB and BOM of the OZY board can be found at: http://openhpsdr.org/support.php
 ''NOTE: Ozymandias is no longer available from TAPR.''

@@ Line 18: / Line 18: @@
 The latest schematic, PCB and BOM of the OZY board can be found at: http://openhpsdr.org/support.html
-''NOTE: Penelope is no longer available from TAPR.''
+''NOTE: Ozymandias is no longer available from TAPR.''
 OZYMANDIAS??? See http://en.wikipedia.org/wiki/Ozymandias_(name)

← Older revision		Revision as of 01:59, 21 September 2010
Line 17:		Line 17:

	The latest schematic, PCB and BOM of the OZY board can be found at: http://openhpsdr.org/support.html		The latest schematic, PCB and BOM of the OZY board can be found at: http://openhpsdr.org/support.html
		+
		+	''NOTE: Penelope is no longer available from TAPR.''

	OZYMANDIAS??? See http://en.wikipedia.org/wiki/Ozymandias_(name)		OZYMANDIAS??? See http://en.wikipedia.org/wiki/Ozymandias_(name)

← Older revision		Revision as of 18:49, 25 January 2010
Line 22:		Line 22:
	[[Ozy Development History]]		[[Ozy Development History]]

−	[[Category:~~Hardware no longer available~~]]	+	[[Category:Ozy\| ]]

← Older revision		Revision as of 17:46, 25 January 2010
Line 21:		Line 21:

	[[Ozy Development History]]		[[Ozy Development History]]
		+
		+	[[Category:Hardware no longer available]]

@@ Line 20: / Line 20: @@
 OZYMANDIAS??? See http://en.wikipedia.org/wiki/Ozymandias_(name)
-==History==
+[[Ozy Development History]]
-−
-[[Image:OZY_PROD1.jpg|thumb|500px|First production board, 5 April 2007]]
-−
-/22/2007: Architecture Changes
-−
-Sync detect and C&C decode now done at the output of the FX2 rather than the Rx FIFO output. This ensures we can control other cards on the Atlas bus in the event that not all clocks are fully defined. This change is necessary so that we can select the 10MHz reference clock from  Gibraltar, Penelope or Mercury and also the 125MHz reference from Penelope or Mercury.   Numerous code tidied up and comments updated. The Verilog diagrams have been updated to reflect the changes.
-−
-/11/2007: Ready for production.
-−
-/10/2006: Initial tests of Ozy V2 indicate all functions are OK - VK6APH.
-−
-/30/2006: All Alpha 2 kits arrived (including VK6APH in Oz).
-−
-/20/2006: All Alpha 2 kits shipped.
-−
-/18/2006: The parts for the Alpha 2 release are in hand and kitted for the test team. The PCBs were shipped today via overnight service, and should arrive Monday, Nov 20. With luck, all Alpha 2 kits should be enroute to the testers the same day.
-−
-/06/2006: The schematic and PCB board layout for REVB of OZY is complete. This revision corrects issues we found in OZY REVA alpha 1 boards. See [[OZY_REVA_ALPHA_REVLIST]] for issues that were corrected.
-−
-/15/2006: All Alpha OZY boards are now working. The Janus FPGA code has been ported and is working correctly. Phil, VK6APH, had the first QSO using the OZY + Janus + Atlas combination on 12th August 2006. Check out of all the I/O functions continues.
-[[Image:PICT1713 08.jpg|thumb|500px|Assembled OZY as of 14 July 2006]]
-/20/2006: OZY Utilities are written to allow firmware download and FPGA upload via USB using libUSB. A C# class library was written to allow the use of libUSB with C# programs and IronPython.
-−
-/10/2006: OZY now has firmware! Work is under way to switch to libUSB instead of the Cypress driver.
-−
-/07/2006: OZY has been completely assembled minus two components, the Dallas serial to 1-Wire converter and a diode on the logic analyzer port (parts on backorder -estimated ship date 07/07/2006). The Cypress CY7C68013A (FX2) enumerates on USB. The I2C EEPROM on board was programmed with a C0 load with VID 0xFFFE and PID 0x0007. The CyUSB.sys driver's inf file was modified to include the VID/PID. Later the LibUSB-Win32 driver will be used instead. The Cyclone II FPGA was loaded with a test program via JTAG and the test program was successfully run. The next task is to load firmware into the FX2 to allow downloading of the FPGA code over USB.
-−
-See [[OZY_REVA_ALPHA_REVLIST]] for proposed additions/changes to the OZY design before it is released for production.
-−
-See [[OZY_REVA_STARTUP]] for notes/issues on debugging/startup of the OZY alpha board.

@@ Line 1: / Line 1: @@
-==OZYmandias - HPSDR Host Interface & Control==
+'''OZY'''mandias - HPSDR Host Interface & Control
-'''General Description:'''
+[[Image:Ozy_12_Feb_2007.jpg|thumb|500px]]
 The OZY was designed by Philip Covington [mailto:p.covington@gmail.com], N8VB.
-The OZY module is an FPGA based interface controller card that provides the input and output connections to the real world. The use of an [[Altera Cyclone FPGA|Altera Cyclone II FPGA]] provides numerous control lines for interfacing the various boards connected to the Atlas backplane.
+[[Image:Ozy_Verilog.jpg|thumb|500px|Block diagrams of the OZY [[Verilog]] code]]
-−
-A block diagram of OZY is shown below.
-−
-[[Image:Ozy_12_Feb_2007.jpg]]
-−
-Block diagrams of the OZY [[Verilog]] code:
-−
-[[Image:Ozy_Verilog.jpg]]
-−
-−
-[[Image:Ozy_Verilog2.jpg]]
-−
 OZY also provides a high speed USB 2.0 interface to the controlling PC. The USB interface uses a Cypress FX2 chip [http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=14&rpn=CY7C68013A] which greatly simplifies the design, development time and effort. The FX2 supports full duplex USB communications at > 30MB/s, which should allow sufficient bandwidth for current and future requirements.
@@ Line 25: / Line 15: @@
 Whilst specifically designed to support the various HPSDR modules the OZY board makes an excellent general purpose FPGA development system. The source code to both the FX2 and FPGA software is available under GPL and the board is very cost competitive compared with other FPGA development systems.
 The latest schematic, PCB and BOM of the OZY board can be found at: http://openhpsdr.org/support.html
@@ Line 31: / Line 20: @@
 OZYMANDIAS??? See http://en.wikipedia.org/wiki/Ozymandias
-'''Current Status:'''
+==History==
-/05/2007: First production board:
-−
-[[Image:OZY_PROD1.jpg]]
 /22/2007: Architecture Changes
@@ Line 54: / Line 41: @@
 /15/2006: All Alpha OZY boards are now working. The Janus FPGA code has been ported and is working correctly. Phil, VK6APH, had the first QSO using the OZY + Janus + Atlas combination on 12th August 2006. Check out of all the I/O functions continues.
-[[Image:PICT1713 08.jpg|frame|400px|Assembled OZY as of 14 July 2006]]
+[[Image:PICT1713 08.jpg|thumb|500px|Assembled OZY as of 14 July 2006]]
 /20/2006: OZY Utilities are written to allow firmware download and FPGA upload via USB using libUSB. A C# class library was written to allow the use of libUSB with C# programs and IronPython.