Phoenix Schematics - Revision history

OZ1HFT: +cat

2010-01-25T18:53:46Z

+cat

VK2NRA: link back, remove blank lines, remove redundant heading

2009-06-09T23:52:20Z

link back, remove blank lines, remove redundant heading

VK2NRA: Schematics moved to Phoenix Schematics: title more in sync with real content of page

2009-05-18T04:38:32Z

Schematics moved to Phoenix Schematics: title more in sync with real content of page

VK6BRO at 12:52, 22 January 2008

2008-01-22T12:52:33Z

VK6BRO: New page: The '''Interface Circuit''' uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes. The '''...

2008-01-22T06:57:03Z

New page: The '''Interface Circuit''' uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes. The '''...

New page

The '''Interface Circuit''' uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.

The '''DDS circuit''' uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.

The '''Mixer/QSD''' is based on various comments and sources.It uses the devices proposed originally.
The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.

The '''QSE''' is similar setup in the opposite direction.

Note that there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.

← Older revision		Revision as of 18:53, 25 January 2010
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	Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.		Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.
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		+	[[Category:Phoenix]]

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-'''Schematics'''
+The root sheet schematic for the [[PHOENIX|Phoenix]] board [[Image:Root_sheet.gif]] gives an idea of the overall layout.
-−
 The root sheet schematic [[Image:Root_sheet.gif]] gives an idea of the overall layout.
-−
-−
 '''Interface Circuit'''
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 The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.
 '''DDS circuit'''
 [[Image:DDS.gif]]
 The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.
 The DDS requires several regulators for best performance. [[Image:DDSpower.gif]]
 '''Mixer/QSD'''[[Image:receiver.gif]]
 The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally.
 The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.
 '''QSE''' [[Image:QSE.gif]]
 The QSE circuit is basically the reverse of the receiver with a low level power amp
 Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.

← Older revision	Revision as of 04:38, 18 May 2009
(No difference)