User:VK2NRA/sandbox - Revision history

VK2NRA: Undo revision 1045 by VK2NRA (Talk) go back to before redirect version

2009-05-09T18:55:43Z

Undo revision 1045 by VK2NRA (Talk) go back to before redirect version

VK2NRA: redirect a temp solution

2009-05-09T05:20:15Z

redirect a temp solution

VK2NRA: /* HPSDR Verilog Class */ remove - moved to sandbox2

2009-05-05T09:48:53Z

‎HPSDR Verilog Class: remove - moved to sandbox2

VK2NRA: /* HPSDR Verilog Class */ nnn

2009-05-05T07:10:19Z

‎HPSDR Verilog Class: nnn

VK2NRA: /* HPSDR Verilog Class */ start table

2009-05-05T04:37:20Z

‎HPSDR Verilog Class: start table

VK2NRA: sort a bit

2009-05-05T03:48:08Z

sort a bit

VK2NRA: pull in Kirk's page

2009-05-04T07:49:47Z

pull in Kirk's page

Show changes

VK2NRA: choices

2009-05-03T05:48:43Z

choices

VK2NRA: poss copyright...

2009-05-03T02:35:36Z

poss copyright...

New page

==Possible Copyright==

Please see the [http://creativecommons.org/licenses/by-sa/3.0/ Creative Commons Share Alike] License.

← Older revision		Revision as of 18:55, 9 May 2009
Line 1:		Line 1:
−	~~#REDIRECT~~ [[Verilog]]	+	== Page for Kirk's Verilog Lecture Series ==
		+
		+	<span class="style1">Test VCD file</span> - use this to test your standalone waveform viewer, such as GTKwave. This file is not needed if you are using Veritak or ModelSim since they have there own built in waveform viewers. For those of you using ModelSim or Veritak, as an exercise, I'd like you to discover whether you can or can't display this VCD file. Please telll me your findings.
		+
		+	[http://verilog.openhpsdr.org/ozyjanus_sim.vcd ozyjanus_sim.vcd] - this is a simulation I did the other day of a new version of ozyjanus.v and other files for the Ozy FPGA.
		+
		+	== Verilog Simulators ==
		+
		+	=== Free versions ===
		+
		+	<span class="style3">[ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ ]</span>[ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ Icarus Verilog simulator] - If you are using Windows try this [http://bleyer.org/icarus/ link] instead
		+
		+	[https://www.altera.com/support/software/download/eda_software/modelsim/dnl-msim-64a-qii90.jsp ModelSim - Altera Starter Edition 6.4a for Windows ] - Windows�Vista (32-bit), and Windows XP (32-bit)
		+
		+	[https://www.altera.com/support/software/download/eda_software/modelsim/dnl-msim-64a-qii90.jsp ModelSim -Altera Starter Edition 6.4a for Linux] - Red Hat Linux Enterprise 4/5, SUSE Linux Enterprise 9 (32-bit)
		+
		+	This [http://verilog.openhpsdr.org/ModelSim Quck Setup.txt short text file] may help you get going on ModeSim 6.3g. I suggest you also read ModelSims tutorial. Let me know if you have any problems or if I wrote something unclear or wrong.
		+
		+	=== Verilog Simulator & Waveform viewer ===
		+
		+	[http://www.sugawara-systems.com Veritak ]<nowiki>: Verilog HDL Compiler/Simulator supporting major Verilog 2001 HDL features. It is integral environment including VHDL to Verilog translator, syntax highlight editor (Veripad), class hierarchy viewer, multiple waveform viewer, source analyzer, and more --available for Windows XP/2000. If you are looking for fast verilog HDL simulator with very good GUI, woth an inexpensive price ($50), this is it. You can try Veritak for free for two weeks. </nowiki>
		+
		+	=== Free VCD Waveform Viewers ===
		+
		+	[http://verilog.openhpsdr.org/gtkwave-1.3.12-setup.exe ]I recommend the GTKwave waveform viewer.
		+
		+	[http://verilog.openhpsdr.org/GTKwave3_1_6.rar GTKwave3_1_6.rar] along with an installation/tutorial video [http://verilog.openhpsdr.org/GTKwaveTutorial.rar GTKwaveTutorial.rar] will show you how to install and run on Windows. Demo was on Win XP. You will also need to download the Test VCD file mentioned above
		+
		+	GTKwave links -http://gtkwave.sourceforge.net/ - for other OS.
		+
		+	Synapticad's free WaveViewer for Windows - http://www.syncad.com/freeviewer.htm - this also installs a bunch of other software that may/may not be usable.
		+
		+
		+
		+	== Altera Quartus ==
		+
		+	[http://verilog.openhpsdr.org/AlteraQuartus_Ozy_Mercury_1280by960_MP4.rar Altera Quartus Lecture] March 16, 2009 Video in MP4 format, 1280 by 960 resolution, 160MB (1hr 45min). Lecture about using Altera Quartus tools and a new Mercury and Ozy design in progress using NWire. See the Merc_Ozy_test.rar.
		+
		+	[http://verilog.openhpsdr.org/AlteraQuartus_Ozy_Mercury_1280by960_WMV.rar Altera Quartus Lecture] March 16, 2009 Video in WMV format, 1280 by 960 resolution, 110MB (1hr 45min).
		+
		+	== Ozy, Mercury Software Handshaking ==
		+
		+	[http://verilog.openhpsdr.org/Handshake_CDC_OzyMercuryOverview_MP4.rar Handshake_CDC_OzyMercuryOverview_MP4.rar] March 19, 2009 Video in MP4 format, 1280 by 960, 126MB (1hr 32 min). Lecture about using handshake logic with respect to CDC and metastability issues, overview of Ozy and some Mercury code and how they communicate using the NWire modules. Brief discussion on data format/blocks of data between PowerSDR and Ozy's TX & RX FIFOs
		+
		+	[http://verilog.openhpsdr.org/Handshake_CDC_OzyMercuryOverview_WMV.rar Handshake_CDC_OzyMercuryOverview_WMV.rar] March 19, 2009 Video in WMV format, 1280 by 960, 124MB (1hr 32 min).
		+
		+	[http://verilog.openhpsdr.org/HPSDR Mar 20 2009.rar HPSDR Mar 20 2009]. Code using NWire for Ozy, Mercury and Penelope. The projects for each have been updated to work with the Altera Quartus 9.0 tools which I will use from now on. The Ozy project now includes sim.v and wave.do. Try to get sim.v running by including all the necessary files in your simulator. Note that there are 3 Altera megafunctions. If your simulator can't include these then please try the new ModelSim - Altera Starter Edition v6.4a. I posted a new link near the beginning of this webpage for both a Windows version and a Linux version of ModelSim. The wave.do is a file containing some of the simulation signals to help get you started if you are using ModelSim.
		+
		+	[http://verilog.openhpsdr.org/HPSDR Mar 21 2009.rar HPSDR Mar 21 2009] Here is a [http://verilog.openhpsdr.org/20Marchcode.JPG picture] reported by Phil Harman VK6APH and [http://verilog.openhpsdr.org/PowerSDR_SR96000.jpg another] reported by Rick Hambly W2GPS showing a bug (spurs) in the audio of the Mar 20 code. In this release I have fixed the bug. I would like for you to try to find the bug and will discuss how to go about it in the Mon. Mar 23 webinar. So please dont look at the new code changes in Tx_fifo_ctrl.v - your first clue as to where the bug is located. See if you can first get the Mar 20 code running, like Rick and Phil did, and verify the bug. Then try to find and fix the bug in Tx_fifo_ctrl.v in the Ozy FPGA. If you need more clues, email me This is a good exercise for what you have learned so far.
		+
		+	[http://verilog.openhpsdr.org/verilog_libs.do verilog_libs.do] Script for those using ModelSim to create/compile various Altera libraries for use in simulation. Only needs to be run once after setting up a ModelSim project. My [http://verilog.openhpsdr.org/sim.do sim.do] script uses these.
		+
		+	[http://verilog.openhpsdr.org/Ozy_USB_interface_1280x960_MP4.rar Ozy_USB_interface_1280x960_MP4.rar] Mar 23, 2009 Video in MP4 format, 1280 x 960 resolution, 151MB (1hr 38min) [http://verilog.openhpsdr.org/Ozy_USB_interface_1280x960_WMV.rar Ozy_USB_interface_1280x960_WMV.rar] Mar 23, 2009 Video in WMV format, 1280 x 960 resolution, 140MB (1hr 38min)
		+
		+	[http://verilog.openhpsdr.org/MercuryReceiver.ppt MercuryReceiver.ppt] Powerpoint slides used in Mar 26 Mercury Receiver lecture presentation by Kirk Weedman
		+
		+	[http://verilog.openhpsdr.org/CIC_Lecture_20090326.wmv CIC filters & Mercury Reciever] Mar 26 2009, WMV format, 91MB, approx 1hr 32min. CIC lecture by Michael Kreeger and Mercury Receiver lecture by Kirk Weedman. Recorded by Michael Kreeger.
		+
		+	[http://verilog.openhpsdr.org/MercuryReceiver_1280by960_MP4.rar CIC filters & Mercury Reciever] Mar 26 2009, MP4 format, 72MB, approx 1hr 27min. CIC lecture by Michael Kreeger & Mercury Receiver lecture by Kirk Weedman. Mar 26 2009, MP4 format recorded by Kirk Weedman. This recording missed some talking between lectures as my computer had to reboot due to a GoToMeeting problem.
		+
		+	[http://verilog.openhpsdr.org/CORDIC Test.rar CORDIC Test] Simple simulation setup for testing cordic.v and kordic.v as shown in the April 8, 2009 webinar. I would like users to test the difference of these two in Mercury and see if they can notice any difference in the quality. Look at Mercury's receiver.v module and search for cordic & kordic and you should see how to use one vs the other.
		+
		+	Note: April 8, 2009 CORDIC webinar: I did not explain something in the kordic.v code that I should have. There are several equations in Stage 0 that are of the following format:
		+
		+	X[0] <= {Xin[WI-1], Xin} << (EXTRA_BITS-1); // since An = 1.647, divide input by 2 and then multiply by 2^EXTRA_BITS<br /> Y[0] <= {Yin[WI-1], Yin} << (EXTRA_BITS-1);
		+
		+	I told you that we divide by 2 then multiply by 2^EXTRA_BITS but I didnt tell you WHY we divide by 2. Notice that the overal gain due to the CORIDC iterative process where the Ki's are removed from each iteration gives us an overall gain of 1.647. Therefore to get the gain back to unity we should multiply by 1/1.647 = .6073. This implementation in kordic.v as well as that of cordic.v takes a simplistic approach and multiples by 1/2 = .5. Not the ideal .6073, but OK. We could get closer to unity by doing something like 1/2+1/16+1/32 = .59375 or maybe something even better.<br /> ---------------------------------------------------------------------------------------------------------------------------------------------
		+
		+	[http://verilog.openhpsdr.org/cordic_MP4.rar CORDIC] Apr 8, 2009, MP4 format, 82MB, approx 1hr 32min. Presentation of CORDIC theory, specifically created a function to do SIN() and COS() multiplication, implementation code in Verilog and simulation. Also how a cordic is used in the Mercury receiver.
		+
		+	[http://verilog.openhpsdr.org/CordicWMV.rar CORDIC] Apr 8, 2009, WMV format, 117MB, approx 1hr 32min.
		+
		+	[http://verilog.openhpsdr.org/HPSDR Apr 13 2009.rar HPSDR Apr 13 2009] Latest test code release. Changes to bus signals due to addition of more code to support Janus in the Ozy FPGA. See MPOJ.ppt for a diagram of many of the bus data transfer signals. Changes to project files to help reduce timing analysis warnings and errors. Misc. code cleanup.
		+
		+	[http://verilog.openhpsdr.org/CDC_Penelope_MP4.rar CDC_Penelope_MP4] April 15 2009 MP4 format, 125MB, approx. 1 hr 45 min. Presentation on communication between Mercury, Penelope, Ozy and Janus, CDC design issues for slow to fast and fast to slow clock domain crossing. Overview and selected discussion of Penelope modules.
		+
		+	[http://verilog.openhpsdr.org/MPOJ.ppt MPOJ.ppt] Block diagram of NWire and I2S communications across the Atlas Bus as shown in the CDC_Penelope webinar
		+
		+	[http://verilog.openhpsdr.org/sim.v sim.v] Latet Ozy_Janus test file.
		+
		+	For now this is the end of the main lectures. I appreciate everyone atending and hope you have a better understanding of Verilog and how you can use it. Also thanks to those that gave feedback. We can still have a webinar every once in a while as the need arises.
		+
		+	Thanks<br /> Kirk Weedman KD7IRS

@@ Line 1: / Line 1: @@
-== Page for Kirk's Verilog Lecture Series ==
+#REDIRECT [[Verilog]]
-−
-<span class="style1">Test VCD file</span> - use this to test your standalone waveform viewer, such as GTKwave. This file is not needed if you are using Veritak or ModelSim since they have there own built in waveform viewers. For those of you using ModelSim or Veritak, as an exercise, I'd like you to discover whether you can or can't display this VCD file. Please telll me your findings.
-−
-[http://verilog.openhpsdr.org/ozyjanus_sim.vcd ozyjanus_sim.vcd] - this is a simulation I did the other day of a new version of ozyjanus.v and other files for the Ozy FPGA.
-−
-== Verilog Simulators ==
-−
-=== Free versions ===
-−
-<span class="style3">[ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ ]</span>[ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ Icarus Verilog simulator] - If you are using Windows try this [http://bleyer.org/icarus/ link] instead
-−
-[https://www.altera.com/support/software/download/eda_software/modelsim/dnl-msim-64a-qii90.jsp ModelSim - Altera Starter Edition 6.4a for Windows ] - Windows�Vista (32-bit), and Windows XP (32-bit)
-−
-[https://www.altera.com/support/software/download/eda_software/modelsim/dnl-msim-64a-qii90.jsp ModelSim -Altera Starter Edition 6.4a for Linux] - Red Hat Linux Enterprise 4/5, SUSE Linux Enterprise 9 (32-bit)
-−
-This [http://verilog.openhpsdr.org/ModelSim Quck Setup.txt short text file] may help you get going on ModeSim 6.3g. I suggest you also read ModelSims tutorial. Let me know if you have any problems or if I wrote something unclear or wrong.
-−
-=== Verilog Simulator & Waveform viewer ===
-−
-[http://www.sugawara-systems.com Veritak ]<nowiki>: Verilog HDL Compiler/Simulator supporting major Verilog 2001 HDL features. It is integral environment including VHDL to Verilog translator, syntax highlight editor (Veripad), class hierarchy viewer, multiple waveform viewer, source analyzer, and more --available for Windows XP/2000. If you are looking for fast verilog HDL simulator with very good GUI, woth an inexpensive price ($50), this is it. You can try Veritak for free for two weeks. </nowiki>
-−
-=== Free VCD Waveform Viewers ===
-−
-[http://verilog.openhpsdr.org/gtkwave-1.3.12-setup.exe ]I recommend the GTKwave waveform viewer.
-−
-[http://verilog.openhpsdr.org/GTKwave3_1_6.rar GTKwave3_1_6.rar] along with an installation/tutorial video [http://verilog.openhpsdr.org/GTKwaveTutorial.rar GTKwaveTutorial.rar] will show you how to install and run on Windows. Demo was on Win XP. You will also need to download the Test VCD file mentioned above
-−
-GTKwave links -http://gtkwave.sourceforge.net/ - for other OS.
-−
-Synapticad's free WaveViewer for Windows - http://www.syncad.com/freeviewer.htm - this also installs a bunch of other software that may/may not be usable.
-−
-−
-−
-== Altera Quartus ==
-−
-[http://verilog.openhpsdr.org/AlteraQuartus_Ozy_Mercury_1280by960_MP4.rar Altera Quartus Lecture] March 16, 2009 Video in MP4 format, 1280 by 960 resolution, 160MB (1hr 45min). Lecture about using Altera Quartus tools and a new Mercury and Ozy design in progress using NWire. See the Merc_Ozy_test.rar.
-−
-[http://verilog.openhpsdr.org/AlteraQuartus_Ozy_Mercury_1280by960_WMV.rar Altera Quartus Lecture] March 16, 2009 Video in WMV format, 1280 by 960 resolution, 110MB (1hr 45min).
-−
-== Ozy, Mercury Software Handshaking ==
-−
-[http://verilog.openhpsdr.org/Handshake_CDC_OzyMercuryOverview_MP4.rar Handshake_CDC_OzyMercuryOverview_MP4.rar] March 19, 2009 Video in MP4 format, 1280 by 960, 126MB (1hr 32 min). Lecture about using handshake logic with respect to CDC and metastability issues, overview of Ozy and some Mercury code and how they communicate using the NWire modules. Brief discussion on data format/blocks of data between PowerSDR and Ozy's TX & RX FIFOs
-−
-[http://verilog.openhpsdr.org/Handshake_CDC_OzyMercuryOverview_WMV.rar Handshake_CDC_OzyMercuryOverview_WMV.rar] March 19, 2009 Video in WMV format, 1280 by 960, 124MB (1hr 32 min).
-−
-[http://verilog.openhpsdr.org/HPSDR Mar 20 2009.rar HPSDR Mar 20 2009]. Code using NWire for Ozy, Mercury and Penelope. The projects for each have been updated to work with the Altera Quartus 9.0 tools which I will use from now on. The Ozy project now includes sim.v and wave.do. Try to get sim.v running by including all the necessary files in your simulator. Note that there are 3 Altera megafunctions. If your simulator can't include these then please try the new ModelSim - Altera Starter Edition v6.4a. I posted a new link near the beginning of this webpage for both a Windows version and a Linux version of ModelSim. The wave.do is a file containing some of the simulation signals to help get you started if you are using ModelSim.
-−
-[http://verilog.openhpsdr.org/HPSDR Mar 21 2009.rar HPSDR Mar 21 2009] Here is a [http://verilog.openhpsdr.org/20Marchcode.JPG picture] reported by Phil Harman VK6APH and [http://verilog.openhpsdr.org/PowerSDR_SR96000.jpg another] reported by Rick Hambly W2GPS showing a bug (spurs) in the audio of the Mar 20 code. In this release I have fixed the bug. I would like for you to try to find the bug and will discuss how to go about it in the Mon. Mar 23 webinar. So please dont look at the new code changes in Tx_fifo_ctrl.v - your first clue as to where the bug is located. See if you can first get the Mar 20 code running, like Rick and Phil did, and verify the bug. Then try to find and fix the bug in Tx_fifo_ctrl.v in the Ozy FPGA. If you need more clues, email me This is a good exercise for what you have learned so far.
-−
-[http://verilog.openhpsdr.org/verilog_libs.do verilog_libs.do] Script for those using ModelSim to create/compile various Altera libraries for use in simulation. Only needs to be run once after setting up a ModelSim project. My [http://verilog.openhpsdr.org/sim.do sim.do] script uses these.
-−
-[http://verilog.openhpsdr.org/Ozy_USB_interface_1280x960_MP4.rar Ozy_USB_interface_1280x960_MP4.rar] Mar 23, 2009 Video in MP4 format, 1280 x 960 resolution, 151MB (1hr 38min) [http://verilog.openhpsdr.org/Ozy_USB_interface_1280x960_WMV.rar Ozy_USB_interface_1280x960_WMV.rar] Mar 23, 2009 Video in WMV format, 1280 x 960 resolution, 140MB (1hr 38min)
-−
-[http://verilog.openhpsdr.org/MercuryReceiver.ppt MercuryReceiver.ppt] Powerpoint slides used in Mar 26 Mercury Receiver lecture presentation by Kirk Weedman
-−
-[http://verilog.openhpsdr.org/CIC_Lecture_20090326.wmv CIC filters & Mercury Reciever] Mar 26 2009, WMV format, 91MB, approx 1hr 32min. CIC lecture by Michael Kreeger and Mercury Receiver lecture by Kirk Weedman. Recorded by Michael Kreeger.
-−
-[http://verilog.openhpsdr.org/MercuryReceiver_1280by960_MP4.rar CIC filters & Mercury Reciever] Mar 26 2009, MP4 format, 72MB, approx 1hr 27min. CIC lecture by Michael Kreeger & Mercury Receiver lecture by Kirk Weedman. Mar 26 2009, MP4 format recorded by Kirk Weedman. This recording missed some talking between lectures as my computer had to reboot due to a GoToMeeting problem.
-−
-[http://verilog.openhpsdr.org/CORDIC Test.rar CORDIC Test] Simple simulation setup for testing cordic.v and kordic.v as shown in the April 8, 2009 webinar. I would like users to test the difference of these two in Mercury and see if they can notice any difference in the quality. Look at Mercury's receiver.v module and search for cordic & kordic and you should see how to use one vs the other.
-−
-Note: April 8, 2009 CORDIC webinar: I did not explain something in the kordic.v code that I should have. There are several equations in Stage 0 that are of the following format:
-−
-X[0] <= {Xin[WI-1], Xin} << (EXTRA_BITS-1); // since An = 1.647, divide input by 2 and then multiply by 2^EXTRA_BITS<br /> Y[0] <= {Yin[WI-1], Yin} << (EXTRA_BITS-1);
-−
-I told you that we divide by 2 then multiply by 2^EXTRA_BITS but I didnt tell you WHY we divide by 2. Notice that the overal gain due to the CORIDC iterative process where the Ki's are removed from each iteration gives us an overall gain of 1.647. Therefore to get the gain back to unity we should multiply by 1/1.647 = .6073. This implementation in kordic.v as well as that of cordic.v takes a simplistic approach and multiples by 1/2 = .5. Not the ideal .6073, but OK. We could get closer to unity by doing something like 1/2+1/16+1/32 = .59375 or maybe something even better.<br /> ---------------------------------------------------------------------------------------------------------------------------------------------
-−
-[http://verilog.openhpsdr.org/cordic_MP4.rar CORDIC] Apr 8, 2009, MP4 format, 82MB, approx 1hr 32min. Presentation of CORDIC theory, specifically created a function to do SIN() and COS() multiplication, implementation code in Verilog and simulation. Also how a cordic is used in the Mercury receiver.
-−
-[http://verilog.openhpsdr.org/CordicWMV.rar CORDIC] Apr 8, 2009, WMV format, 117MB, approx 1hr 32min.
-−
-[http://verilog.openhpsdr.org/HPSDR Apr 13 2009.rar HPSDR Apr 13 2009] Latest test code release. Changes to bus signals due to addition of more code to support Janus in the Ozy FPGA. See MPOJ.ppt for a diagram of many of the bus data transfer signals. Changes to project files to help reduce timing analysis warnings and errors. Misc. code cleanup.
-−
-[http://verilog.openhpsdr.org/CDC_Penelope_MP4.rar CDC_Penelope_MP4] April 15 2009 MP4 format, 125MB, approx. 1 hr 45 min. Presentation on communication between Mercury, Penelope, Ozy and Janus, CDC design issues for slow to fast and fast to slow clock domain crossing. Overview and selected discussion of Penelope modules.
-−
-[http://verilog.openhpsdr.org/MPOJ.ppt MPOJ.ppt] Block diagram of NWire and I2S communications across the Atlas Bus as shown in the CDC_Penelope webinar
-−
-[http://verilog.openhpsdr.org/sim.v sim.v] Latet Ozy_Janus test file.
-−
-For now this is the end of the main lectures. I appreciate everyone atending and hope you have a better understanding of Verilog and how you can use it. Also thanks to those that gave feedback. We can still have a webinar every once in a while as the need arises.
-−
-Thanks<br /> Kirk Weedman KD7IRS

← Older revision		Revision as of 09:48, 5 May 2009
Line 31:		Line 31:
	Synapticad's free WaveViewer for Windows - http://www.syncad.com/freeviewer.htm - this also installs a bunch of other software that may/may not be usable.		Synapticad's free WaveViewer for Windows - http://www.syncad.com/freeviewer.htm - this also installs a bunch of other software that may/may not be usable.

−	~~== HPSDR Verilog Class ==~~

−	~~by Kirk Weedman KD7IRS~~
−
−	~~{\| class="wikitable"~~
−	\|-
−	~~! width="500"\|Lecture Title~~
−	~~! width="100"\|WMV format~~
−	~~! width="100"\|MP4 format~~
−	~~! width="100"\|Lecture notes and Labs~~
−	\|-
−	~~\| Lecture 1 title and a short description of content.~~
−	~~\| [http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar *]~~
−	~~\| [http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar *]~~
−	~~\| [http://verilog.openhpsdr.org/Lab1.rar *]~~
−	\|-
−	~~\| Lecture 2 title and a short description of content~~
−	~~\| [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]~~
−	~~\| [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]~~
−	~~\| [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]~~
−	\|-
−	~~\| title~~
−	\|
−	\|
−	\|
−	\|}
−
−	[http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar Lecture 2] - Video in MP4 format, 1280 x 720 resolution, 64MB. Only problem is it also recorded my chat window which sometimes blocked the powerpoint but hopefully its OK.
−
−	~~[http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar Lecture 2] - Video in WMV, 28MB - no chat window on screen~~
−
−	~~[http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar Lecture 2] - iPhone video...just had to try this, 53MB, 480 x 320 resolution~~
−
−	~~[http://verilog.openhpsdr.org/Lab2.rar Lab 2] instructions and all labs for Lecture 2~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_03_1280by960.rar Lecture 3 ] - Video in MP4 format, 1280 x 960 resolution, 65MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lab3.rar Lab 3 ] instructions and all labs for Lecture 3~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_04_1280by960_MP4.rar Lecture 4 ] - Video in MP4 format, 1280 x 960 resolution, 85MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lab4.rar ][http://verilog.openhpsdr.org/Lecture_04_1280by960_WMV.rar Lecture 4 ] - Video in WMV format, 1280 x 960 resolution, 123MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lab4.rar Lab 4] instructions and all labs for Lecture 4~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_05_1280by960_MP4.rar Lecture 5 ] - Video in MP4 format, 1280 x 960 resolution, 65MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lab4.rar ][http://verilog.openhpsdr.org/Lecture_05_1280by960_WMV.rar Lecture 5 ] - Video in WMV format, 1280 x 960 resolution, 90MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lab5.rar Lab 5] instructions and all labs for Lecture 5~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_06_1280by960_MP4.rar Lecture 6 ] - Video in MP4 format, 1280 x 960 resolution, 43MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_06_1280by960_WMV.rar Lecture 6 ] - Video in WMV format, 1280 x 960 resolution, 64MB.~~
−
−	~~[http://verilog.openhpsdr.org/Lab6.rar Lab 6 ] instructions and all labs for Lecture 6~~
−
−	~~[http://verilog.openhpsdr.org/VerilogLecture07_20080223.rar Lecture 7 ] - Video in WMV format, 1280 x 960 resolution, 32MB. Thanks to Michael Kreeger since I had an audio problem with my recording~~
−
−	~~Lecture 7 - Having problems trying to convert WMV to MP4. If anyone can do this please let me know.~~
−
−	~~[http://verilog.openhpsdr.org/Lab7.rar Lab 7 ] instructions and all labs for Lecture 7~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_08_1280by960_MP4.rar Lecture 8 ] - Video in MP4 format, 1280 x 960 resolution, 116MB (1 hr 39min)~~
−
−	~~[http://verilog.openhpsdr.org/Lab8.rar ][http://verilog.openhpsdr.org/Lecture_08_1280by960_WMV.rar Lecture 8 ] - Video in WMV format, 1280 x 960 resolution, 132MB (1 hr 39min)~~
−
−	~~[http://verilog.openhpsdr.org/Lab8.rar Lab 8 ]instructions and all labs for Lecture 8~~
−
−	~~[http://verilog.openhpsdr.org/OneWire.rar OneWire] Verilog code as discussed during Lecture 7 & 8 & 9 videos~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_09_1280by960_MP4.rar Lecture 9 ] - Video in MP4 format, 1280 x 960 resolution, 105MB (1 hr 32min)~~
−
−	~~[http://verilog.openhpsdr.org/lecture_09_1280by960_WMV.rar Lecture 9 ] - Video in WMV format, 1280 x 960 resolution, 146MB (1 hr 32min)~~
−
−	~~[http://verilog.openhpsdr.org/Lab9.rar Lab 9 ]instructions and all labs for Lecture 9~~
−
−	~~Verilog 1995 vs 2001 [http://verilog.openhpsdr.org/2000-HDLCon-presentation_Verilog-2000.pdf document] - Please read this document so you know about some of the new features of Verilog 2001~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_10_1280by960_MP4.rar Lecture 10 ] - Video in MP4 format, 1280 x 960 resolution, 75MB (1hr 14min)~~
−
−	~~[http://verilog.openhpsdr.org/Lecture_10_1280by960_WMV.rar Lecture 10 ] - Video in WMV format, 1280 x 960 resolution, 101MB (1hr 14min)~~
−
−	~~[http://verilog.openhpsdr.org/Lab10.rar Lab 10 ]instructions and all labs for Lecture 10~~
−
−	~~[http://verilog.openhpsdr.org/OneWire.rar ]Here are some reference materials Peter Hughes N7BMG gave me that he downloaded from the internet. I thought these may be of interest.~~
−
−	~~[http://verilog.openhpsdr.org/verilog_2001_ref_guide.pdf verilog_2001_ref_guide.pdf]~~
−
−	~~[http://verilog.openhpsdr.org/verilog_quikref.pdf verilog_quikref.pdf]~~
−
−	~~[http://verilog.openhpsdr.org/VerilogQuickRef.pdf VerilogQuickRef.pdf]~~

	== Altera Quartus ==		== Altera Quartus ==

@@ Line 48: / Line 48: @@
 |-
 |  Lecture 2 title and a short description of content
-|  [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar *]
+|  [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]
-|  [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar Sometimes blocked by chat window which, hopefully it's OK.]
+|  [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]
-|  [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
+|  [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
 |}

@@ Line 35: / Line 35: @@
 by Kirk Weedman KD7IRS
-[http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar Lecture 1] Video in WMV format[http://verilog.openhpsdr.org/lab1.2.rar ]
+{| class="wikitable"
+|-
-[http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar Lecture 1] Video in MP4 format
+!  width="500"|Lecture Title
+!  width="100"|WMV format
-[http://verilog.openhpsdr.org/Lab1.rar  Lab 1] instructions and all labs for Lecture 1
+!  width="100"|MP4 format
 [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar Lecture 2] - Video in MP4 format, 1280 x 720 resolution, 64MB. Only problem is it also recorded my chat window which sometimes blocked the powerpoint but hopefully its OK.

← Older revision		Revision as of 05:48, 3 May 2009
Line 1:		Line 1:
−	==Possible ~~Copyright~~==	+	==Possible Copyrights==

−	~~Please see the~~ [http://creativecommons.org/licenses/by-sa/3.0/ Creative Commons Share Alike] ~~License~~.	+	[http://creativecommons.org/licenses/by-sa/3.0/ Creative Commons Share Alike]
		+
		+	[http://www.gnu.org/copyleft/fdl.html GNU Free Documentation License]