User:VK2NRA/sandbox2 - Revision history

VK2NRA: add source column

2009-08-10T00:00:14Z

add source column

VK2NRA: final

2009-08-09T23:49:52Z

final

VK2NRA: table layout

2009-08-09T23:35:12Z

table layout

VK2NRA: x

2009-05-12T04:59:18Z

VK2NRA: make empty

2009-05-11T11:54:51Z

make empty

VK2NRA: bit more

2009-05-11T11:46:50Z

bit more

VK2NRA: /* HPSDR Verilog Lectures */ start filling from Graham's email

2009-05-09T19:37:24Z

‎HPSDR Verilog Lectures: start filling from Graham's email

VK2NRA: lectures...

2009-05-05T09:26:23Z

lectures...

New page

== HPSDR Verilog Lectures ==

by Kirk Weedman KD7IRS

{| class="wikitable"
|-
! width="500"|Lecture Title
! width="100"|WMV format
! width="100"|MP4 format
! width="100"|Lecture notes and Labs
|-
| Lecture 1 title and a short description of content.
| [http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar *]
| [http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar *]
| [http://verilog.openhpsdr.org/Lab1.rar *]
|-
| Lecture 2 title and a short description of content
| [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]
| [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]
| [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
|-
| title
|
|
|
|}

----------------------------

[http://verilog.openhpsdr.org/Lecture_03_1280by960.rar Lecture 3 ] - Video in MP4 format, 1280 x 960 resolution, 65MB.

[http://verilog.openhpsdr.org/Lab3.rar Lab 3 ] instructions and all labs for Lecture 3

[http://verilog.openhpsdr.org/Lecture_04_1280by960_MP4.rar Lecture 4 ] - Video in MP4 format, 1280 x 960 resolution, 85MB.

[http://verilog.openhpsdr.org/Lab4.rar ][http://verilog.openhpsdr.org/Lecture_04_1280by960_WMV.rar Lecture 4 ] - Video in WMV format, 1280 x 960 resolution, 123MB.

[http://verilog.openhpsdr.org/Lab4.rar Lab 4] instructions and all labs for Lecture 4

[http://verilog.openhpsdr.org/Lecture_05_1280by960_MP4.rar Lecture 5 ] - Video in MP4 format, 1280 x 960 resolution, 65MB.

[http://verilog.openhpsdr.org/Lab4.rar ][http://verilog.openhpsdr.org/Lecture_05_1280by960_WMV.rar Lecture 5 ] - Video in WMV format, 1280 x 960 resolution, 90MB.

[http://verilog.openhpsdr.org/Lab5.rar Lab 5] instructions and all labs for Lecture 5

[http://verilog.openhpsdr.org/Lecture_06_1280by960_MP4.rar Lecture 6 ] - Video in MP4 format, 1280 x 960 resolution, 43MB.

[http://verilog.openhpsdr.org/Lecture_06_1280by960_WMV.rar Lecture 6 ] - Video in WMV format, 1280 x 960 resolution, 64MB.

[http://verilog.openhpsdr.org/Lab6.rar Lab 6 ] instructions and all labs for Lecture 6

[http://verilog.openhpsdr.org/VerilogLecture07_20080223.rar Lecture 7 ] - Video in WMV format, 1280 x 960 resolution, 32MB. Thanks to Michael Kreeger since I had an audio problem with my recording

Lecture 7 - Having problems trying to convert WMV to MP4. If anyone can do this please let me know.

[http://verilog.openhpsdr.org/Lab7.rar Lab 7 ] instructions and all labs for Lecture 7

[http://verilog.openhpsdr.org/Lecture_08_1280by960_MP4.rar Lecture 8 ] - Video in MP4 format, 1280 x 960 resolution, 116MB (1 hr 39min)

[http://verilog.openhpsdr.org/Lab8.rar ][http://verilog.openhpsdr.org/Lecture_08_1280by960_WMV.rar Lecture 8 ] - Video in WMV format, 1280 x 960 resolution, 132MB (1 hr 39min)

[http://verilog.openhpsdr.org/Lab8.rar Lab 8 ]instructions and all labs for Lecture 8

[http://verilog.openhpsdr.org/OneWire.rar OneWire] Verilog code as discussed during Lecture 7 & 8 & 9 videos

[http://verilog.openhpsdr.org/Lecture_09_1280by960_MP4.rar Lecture 9 ] - Video in MP4 format, 1280 x 960 resolution, 105MB (1 hr 32min)

[http://verilog.openhpsdr.org/lecture_09_1280by960_WMV.rar Lecture 9 ] - Video in WMV format, 1280 x 960 resolution, 146MB (1 hr 32min)

[http://verilog.openhpsdr.org/Lab9.rar Lab 9 ]instructions and all labs for Lecture 9

Verilog 1995 vs 2001 [http://verilog.openhpsdr.org/2000-HDLCon-presentation_Verilog-2000.pdf document] - Please read this document so you know about some of the new features of Verilog 2001

[http://verilog.openhpsdr.org/Lecture_10_1280by960_MP4.rar Lecture 10 ] - Video in MP4 format, 1280 x 960 resolution, 75MB (1hr 14min)

[http://verilog.openhpsdr.org/Lecture_10_1280by960_WMV.rar Lecture 10 ] - Video in WMV format, 1280 x 960 resolution, 101MB (1hr 14min)

[http://verilog.openhpsdr.org/Lab10.rar Lab 10 ]instructions and all labs for Lecture 10

[http://verilog.openhpsdr.org/OneWire.rar ]Here are some reference materials Peter Hughes N7BMG gave me that he downloaded from the internet. I thought these may be of interest.

[http://verilog.openhpsdr.org/verilog_2001_ref_guide.pdf verilog_2001_ref_guide.pdf]

[http://verilog.openhpsdr.org/verilog_quikref.pdf verilog_quikref.pdf]

[http://verilog.openhpsdr.org/VerilogQuickRef.pdf VerilogQuickRef.pdf]

@@ Line 2: / Line 2: @@
 |-
 !  width="300"|Part Name
 !  width="100" align="right"|Price ($US)
 |-
 |Antec NSK2480 Case and power supply
 |align="right"|100.00
 |-
 |Intel DQ45EK Desktop Board
 |align="right"|130.00
 |-
 |Intel Core2 Duo CPU and Fan Assembly
 |align="right"|69.00
 |-
 |Solid State Disk Drive 32GB
 |align="right"|109.00
 |-
 |External Optical Drive
 |align="right"|99.99
 |-
 |Virtual Audio Cable
 |align="right"|39.99
 |}

@@ Line 1: / Line 1: @@
-{| class="wikitable"
+{| class="wikitable" cellpadding="0"
 |-
 !  width="300"|Part Name
-!  width="100"|Price ($US)
+!  width="100" align="right"|Price ($US)
 |-
 |Antec NSK2480 Case and power supply
-|100
+|align="right"|100.00
 |-
 |Intel DQ45EK Desktop Board
-|130
+|align="right"|130.00
 |-
 |Intel Core2 Duo CPU and Fan Assembly
-|69
+|align="right"|69.00
 |-
 |Solid State Disk Drive 32GB
-|109
+|align="right"|109.00
 |-
 |External Optical Drive
-|99.99
+|align="right"|99.99
 |-
 |Virtual Audio Cable
-|39.99
+|align="right"|39.99
 |}

← Older revision		Revision as of 23:35, 9 August 2009
Line 1:		Line 1:
−	~~== HPSDR Verilog Lectures ==~~
−
−	~~by Kirk Weedman KD7IRS~~
−
	{\| class="wikitable"		{\| class="wikitable"
	\|-		\|-
−	! width="~~500~~"\|~~Lecture Title~~	+	! width="300"\|Part Name
−	! width="100"\|~~WMV format~~	+	! width="100"\|Price ($US)
−	~~! width="100"\|MP4 format~~	+
−	~~! width="100"\|Lecture notes and Labs~~	+
	\|-		\|-
−	\| ~~Lecture~~	+	\|Antec NSK2480 Case and power supply
−	\|	+	\|100
−	\|	+
−	\|	+
	\|-		\|-
−	\|	+	\|Intel DQ45EK Desktop Board
−	\|	+	\|130
−	\|	+
−	\|	+
	\|-		\|-
−	\|	+	\|Intel Core2 Duo CPU and Fan Assembly
−	\|	+	\|69
−	\|	+
−	\|	+
	\|-		\|-
−	\|	+	\|Solid State Disk Drive 32GB
−	\|	+	\|109
−	\|	+
−	\|	+
	\|-		\|-
−	\|	+	\|External Optical Drive
−	\|	+	\|99.99
−	\|	+	\|-
−	\|	+	\|Virtual Audio Cable
		+	\|39.99
	\|}		\|}
−
−
−	~~----------------------------~~

@@ Line 10: / Line 10: @@
 !  width="100"|Lecture notes and Labs
 |-
-|  Lecture 1: Verilog as a Hardware Description Language (HDL) Overview, Introduction, Syntax and Rules.
+| Lecture 4: Non-Blocking Assignments, and much more on Simulation Process
-|  [http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar *]
-|  [http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar *]
-|  [http://verilog.openhpsdr.org/Lab1.rar *]
 |-
-|  Lecture 2: The Verilog Hardware Description Language. Registers, Assignments, Operators, Statements, Functions, Tasks.
-|  [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]
-|  [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]
-|  [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
 |-
+|
-| [http://verilog.openhpsdr.org/Lecture_03_1280by960.rar 65MB]
-| [http://verilog.openhpsdr.org/Lab3.rar Labs]
 |-
-| Lecture 4: Non-Blocking Assignments, and much more on Simulation Process
+|
+|
@@ Line 32: / Line 37: @@
 ----------------------------

@@ Line 22: / Line 22: @@
 |  Lecture 3: What Good is Verilog? Programming Structure, Concurrent Processes, and The Notion of Time, Blocking Assignments, and The Simulation Process.
+|
+|
+|