Verilog - Revision history

OZ1HFT: +cat

2010-01-25T18:03:40Z

+cat

VK2NRA: add 10

2009-05-12T05:04:11Z

add 10

VK2NRA: more lectures

2009-05-12T04:58:16Z

more lectures

VK2NRA: more lectures

2009-05-12T04:47:18Z

more lectures

VK2NRA: start inserting table of lectures

2009-05-11T11:50:38Z

start inserting table of lectures

VK2NRA: improvements from Graham - a work in progress

2009-05-09T19:13:21Z

improvements from Graham - a work in progress

VK2NRA: sp it right!

2009-05-05T11:57:23Z

sp it right!

VK2NRA at 09:12, 5 May 2009

2009-05-05T09:12:55Z

VK2NRA: start verilog page(s)

2009-05-05T09:11:14Z

start verilog page(s)

New page

'''Verilog''' is a hardware description language used to model processes in the FPGAs of several HPSDR boards.

A course was presented by Kirk Wickland. It cosisted of ten one hour recorded lectures on how to program in Verilog,
including tools usage, and another five lectures on code walk-throughs for the code inside of [[MERCURY|Mercury]], [[PENELOPE|Penelope]], [[OZY|Ozy]], and the signal flows
between them.

The lectures are available at [http://varilog.opensdr.org/ http://varilog.opensdr.org/].

← Older revision		Revision as of 18:03, 25 January 2010
Line 67:		Line 67:

	The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].		The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].
		+
		+	[[Category:Developer resources]]

@@ Line 55: / Line 55: @@
 | [http://verilog.openhpsdr.org/Lab8.rar Labs]
 |-
-| Lecture 9: Synthesis Technology. Code walk through and simulation of the "N-Wire" Protocol. The Synthesis Process, Abstraction Levels, Register Transfer
+| Lecture 9: Synthesis Technology. Code walk through and simulation of the "N-Wire" Protocol. The Synthesis Process, Abstraction Levels, Register Transfer Language (RTL), Guidelines, Operators, Statements, Indexes, Inference, Resetting, Synchronous and Asynchronous Circuits.
 | [http://verilog.openhpsdr.org/lecture_09_1280by960_WMV.rar 146MB]
 | [http://verilog.openhpsdr.org/Lecture_09_1280by960_MP4.rar 105MB]
 | [http://verilog.openhpsdr.org/Lab9.rar Labs]
 |}
 The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].

@@ Line 44: / Line 44: @@
 | [http://verilog.openhpsdr.org/Lecture_06_1280by960_MP4.rar 43 MB]
 | [http://verilog.openhpsdr.org/Lab6.rar Labs]
 |}
 The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].

@@ Line 29: / Line 29: @@
 | [http://verilog.openhpsdr.org/Lecture_03_1280by960.rar 65MB]
 | [http://verilog.openhpsdr.org/Lab3.rar Labs]
 |}
 The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].

← Older revision		Revision as of 11:50, 11 May 2009
Line 8:		Line 8:
	Lectures 11 through 16 are special topics, focusing on the Verilog code as used inside of Mercury, Ozy, and Penelope, issues, and improvements being developed by Kirk for communicating between the modules, which all are in separate clock domains.		Lectures 11 through 16 are special topics, focusing on the Verilog code as used inside of Mercury, Ozy, and Penelope, issues, and improvements being developed by Kirk for communicating between the modules, which all are in separate clock domains.

−	The lectures ~~are~~ available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].	+	{\| class="wikitable"
		+	\|-
		+	! width="500"\|Lecture Title
		+	! width="100"\|WMV format
		+	! width="100"\|MP4 format
		+	! width="100"\|Lecture notes and Labs
		+	\|-
		+	\| Lecture 1: Verilog as a Hardware Description Language (HDL) Overview, Introduction, Syntax and Rules.
		+	\| [http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar *]
		+	\| [http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar *]
		+	\| [http://verilog.openhpsdr.org/Lab1.rar *]
		+	\|-
		+	\| Lecture 2: The Verilog Hardware Description Language. Registers, Assignments, Operators, Statements, Functions, Tasks.
		+	\| [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]
		+	\| [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]
		+	\| [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
		+	\|-
		+	\| Lecture 3: What Good is Verilog? Programming Structure, Concurrent Processes, and The Notion of Time, Blocking Assignments, and The Simulation Process.
		+	\|
		+	\| [http://verilog.openhpsdr.org/Lecture_03_1280by960.rar 65MB]
		+	\| [http://verilog.openhpsdr.org/Lab3.rar Labs]
		+	\|}
		+
		+	The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].

@@ Line 1: / Line 1: @@
 '''Verilog''' is a hardware description language used to model processes in the FPGAs of several HPSDR boards.
-A course was presented by Kirk Weedman. It cosisted of ten one hour recorded lectures on how to program in Verilog,
+A course was presented by Kirk Weedman. It consisted of ten one hour recorded lectures on how to program in Verilog,
-including tools usage, and another five lectures on code walk-throughs for the code inside of [[MERCURY|Mercury]], [[PENELOPE|Penelope]], [[OZY|Ozy]], and the signal flows
+including tools usage, and another five lectures on code walk-throughs for the code inside of [[MERCURY|Mercury]], [[PENELOPE|Penelope]], [[OZY|Ozy]], and the signal flows between them. Many lectures have an additional half hour of demonstrations or examples of the programming and simulation tools in the context of the lecture's topics.
 between them.
 The lectures are available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].

← Older revision		Revision as of 09:12, 5 May 2009
Line 5:		Line 5:
	between them.		between them.

−	The lectures are available at [http://~~varilog~~.~~opensdr~~.org/ http://~~varilog~~.~~opensdr~~.org/].	+	The lectures are available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].