HPSDR Firmware Loading
The Current version of the Firmware can be found on the Downloads section of the website is Downloads
The verilog code for each of the Field Programmable Gate Arrays (FPGA) is compiled with ALtera program call Quartus II. A version of the code is availabe for download if you want to modify or develop new verilog code. On this wiki, there is a set of videos introducing verilog code practice using examples from the verilog code in the HPSDR boards.
Only boards that are directly connected to the computer (JTAG connector, USB or ethernet) can easily load firmware. Since we have a FPGA on these boards we can program them to function as JTAG programmers.
Lets explore the options.
Direct JTAG programming
Quartus is a full verilog development environment with a code simulator. The download of this code is over 10 GB so it is generally unreasonable if you have not intention of developing verilog code. This software does have the ability to program the FPGA directly with additional hardware connector.
- Parallel Port Bitblaster - This hardware use the parallel port found of old computers and often used as a printer port.
- USB Bitblaster - There are many of these USB BitBlasters, which operate through the USB port. Many third party versions of this devicxe are available on the internet.
- Ethernet Bitblaster - We are aware that these exist but they seem to be quite expensive at this time.
Ozy or Magisters's Firmware
The OzyJanus firmware is load directly by the radio software each time the radio software program is started.
USB JTAG programmer
Ozy or Magister as a USB Programmer
Ozy JTAG Blaster is an attempt to use existing HPSDR hardware as a bitblaster. This system was allows the programming of the Mercury and Penelope with and Ozy or Magister board. The approach depends on a software program from Altera and a windows batch file to setup your commands. This approach only works from windows computers