Difference between revisions of "METIS"

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(New page: ''' == OzyII - (AussieII) A high speed PC interface == ''' Project Leader: Phil VK6APH)
 
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== OzyII - (AussieII) A high speed PC interface ==
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== OzyII - (Aussie II) A high speed PC interface ==
 
'''  
 
'''  
  
Project Leader: Phil VK6APH
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Project Leader: TBA
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Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.
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Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.
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Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.
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User input relating to the design and features is requested via the HPSDR reflector.

Revision as of 00:22, 11 April 2009

OzyII - (Aussie II) A high speed PC interface

Project Leader: TBA

Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.

Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.

Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.

User input relating to the design and features is requested via the HPSDR reflector.