Difference between revisions of "METIS"
From HPSDRwiki
(→OzyII - (Aussie II) A high speed PC interface: change section to bold to eliminate double header, link to old Ozy) |
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| − | + | '''OzyII''' (or maybe Aussie II?) will be a high speed PC interface. Whilst the original [[OZY|Ozy]] board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC. | |
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| − | Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC. | + | |
Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces. | Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces. | ||
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User input relating to the design and features is requested via the HPSDR reflector. | User input relating to the design and features is requested via the HPSDR reflector. | ||
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| + | Project Leader: TBA | ||
Revision as of 01:12, 1 June 2009
OzyII (or maybe Aussie II?) will be a high speed PC interface. Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.
Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.
Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.
User input relating to the design and features is requested via the HPSDR reflector.
Project Leader: TBA
