PENELOPE - Companion Exciter to Mercury
NOTE: Penelope is no longer available from TAPR. It is now being manufactured by Gerd, DJ8AY. Please contact him at g.loch@nt_electronics.de for further details.
11th February 2009 - The as built construction documents Schematic, PCB and BOM files for Penelope can be found at http://openhpsdr.org/support.html
12th November 2008 = Removed non-commercial restriction from licensed materials, available on hamsdr.
- PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=910
- Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=909
23rd May 2008 - Production board - Wide band spurious output by John N8UR. Penelope producing 0.25w out on 14.1MHz
23rd May 2008 - Production Board - Phase noise plot by John N8UR. Penelope producing 0.25w out on 14.1MHz and phase locked to on board 10MHz TCXO.
14th November 2007 - Wide band noise floor measured by Greg, ZL3IX, at -147dBc/Hz. Design sign off and ready for production.
28th September 2007 - Measurements commenced. Below is screen shot showing IMD performance at 0.5w output on 20m (Image by Greg, ZL3IX)
3rd September 2007 - Added photo of assembled Alpha 2 board
1st September 2007 - Alpha 2 PCB assembled and tested 100% OK - VK6APH
15th August 2007 - Alpha 2 kits all shipped today.
11th August 2007 - Alpha 2 kits are ready to ship except for three (3) parts due on the 14th. Added photos of bare boards (below).
2nd August 2007 - Alpha 2 files uploaded. Alpha 2 parts have been ordered and kits are expected to ship out by the 15th of this month.
- PCB files : http://www.hamsdr.com/personaldirectory.aspx?id=639
- Schematic : http://www.hamsdr.com/personaldirectory.aspx?id=638
- Costed BOM : had errors, deleted
12th May 2007 - Updated Verilog block diagram.
7th May 2007 - Added ALC code, updated Verilog block diagram.
3rd May 2007 - Alpha PCB working, V2 PCB presently being layed out, block diagram updated to reflect latest changes.
19th April 2007 - Alpha 1 kits sent to Penelope testers!
14th April 2007 - Added Alpha 1 Notes at bottom of this page to track errors and lessons learned.
13th April 2007 - Bare PCBs received! Photo below.
5th April 2007 - Update.
- PCB files : see August 2nd, above.
- TAPR Board Approved Penelope Alpha 1 funding! Five (5) sets of parts and PCBs ordered today.
1st April 2007 - Added Verilog block diagram.
30th March 2007 - Update. PCB Layout edits and corrections : (replaced 05 Apr 2007)
29th March 2007 - Update. PCB Layout has many minor edits and corrections : (replaced 30 Mar 2007)
28th March 2007 - Update.
- Block diagram updated to reflect prototype PCB layout.
- Updated Alpha schematic (XA13) for Penelope is here : see August 2nd, above.
- Initial PCB Layout posted here: see August 2nd, above.
- Initial BOM posted here: see August 2nd, above.
17th February 2007 - Update. Block diagram updated to reflect latest schematic.
14th February 2007: Preliminary Alpha schematic (XA8) for Penelope is here : (replaced 28 Mar 2007)
8th February 2007 - Update. Block diagram updated to reflect current Breadboard design.
7th February 2007 - Update. Block diagram updated to reflect design feedback. Breadboard built, tested and working. Prototype PCB layout started.
3rd February 2007 - Initial Specification
The Atlas compatible transmitter will use Digital Up Conversion (DUC) techniques and process the I and Q signal from the PC (or Sasquatch DSP board) directly without the need for a sound card.
Some of the planned features include:
1.8 - 55MHz frequency coverage 0.5W pep output Low level transverter output AM, C-AM, FM, CW, PSK etc RF phase and magnitude outputs for future Envelope Elimination and Restoration (EER) power amplifier Open drain FET for PTT control of external amplifiers Seven open collector outputs for Linear, relay etc control, Optional on board microphone ADC or use with a Janus card Frequency options: o On board high performance 125MHz crystal oscillator o External 125MHz source o On board oscillator can be phase locked to 10MHz reference e.g. Gibraltar o On board 10MHz OCXO/TCXO option FPGA based DUC enabling future code upgrades USB interface to PC via Ozy board I and Q balanced adjustment not required due to digital generation of RF waveform ADC for ALC or PA linearization etc. ALC processed in the FPGA to avoid delays associated with PC processing
Lyle, KK7P, has kindly agreed to lay out the PCB. Please provide feedback, comments and feature requests via the hpsdr reflector.
A block diagram is shown below.
Verilog block diagram
Photo of Assembled Alpha 2 Board
Alpha 1 Notes:
This section will contain notes as we build and learn the mistakes made on Alpha 1.
14th April 2007: EP2C8 pinout error. Pin 36 mistakenly made an IO, it is GND. Cut trace near pin 36. Add short jumper pin 36 to pin 38 (GND). Add short jumper trace side of cut to pin 41. Use pin 41 as DACCLK.
23rd April 2007:
- U31 pin 3 not connected to 3V3. Jumper to U36.
- L27 doesn't pick up 3V3. Jumper to U36.
- U11 pin 2 not grounded. Jumper to C41 or C50.
- PCB silkscreen doesn't show pin 1 on Hittite switches. U9 - lower left. U12 - upper right. Right hand bank of filter switches: lower right. Left hand bank of filter switches: upper left.