Difference between revisions of "Phoenix Schematics"

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'''Schematics'''
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The root sheet schematic for the [[PHOENIX|Phoenix]] board [[Image:Root_sheet.gif]] gives an idea of the overall layout.
 
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The root sheet schematic [[Image:Root_sheet.gif]] gives an idea of the overall layout.
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'''Interface Circuit'''
 
'''Interface Circuit'''
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The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.
 
The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.
 
 
  
 
'''DDS circuit'''  
 
'''DDS circuit'''  
 
[[Image:DDS.gif]]
 
[[Image:DDS.gif]]
 
The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.
 
The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.
 
  
 
The DDS requires several regulators for best performance. [[Image:DDSpower.gif]]
 
The DDS requires several regulators for best performance. [[Image:DDSpower.gif]]
 
 
  
 
'''Mixer/QSD'''[[Image:receiver.gif]]
 
'''Mixer/QSD'''[[Image:receiver.gif]]
 
The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally.
 
The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally.
 
The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.
 
The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.
 
 
  
 
'''QSE''' [[Image:QSE.gif]]
 
'''QSE''' [[Image:QSE.gif]]
 
The QSE circuit is basically the reverse of the receiver with a low level power amp
 
The QSE circuit is basically the reverse of the receiver with a low level power amp
 
  
 
Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.
 
Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.
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[[Category:Phoenix]]

Latest revision as of 11:53, 25 January 2010

The root sheet schematic for the Phoenix board Root sheet.gif gives an idea of the overall layout.

Interface Circuit

Interface.gif

The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.

DDS circuit DDS.gif The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.

The DDS requires several regulators for best performance. DDSpower.gif

Mixer/QSDReceiver.gif The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally. The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.

QSE QSE.gif The QSE circuit is basically the reverse of the receiver with a low level power amp

Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.