Phoenix Schematics

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The root sheet schematic for the Phoenix board Root sheet.gif gives an idea of the overall layout.

Interface Circuit


The interface Circuit uses a small CPLD as in the other HPSDR modules to map to the bus in a programmable way. It will also allow experimentation with various clock schemes.

DDS circuit DDS.gif The DDS circuit uses the latest device from Analog Devices - the AD9912. This has better SFDR and output freq range than previous devices. I have elected to use a PECL driver for the CPLD and a packaged LPF for convenience.

The DDS requires several regulators for best performance. DDSpower.gif

Mixer/QSDReceiver.gif The Mixer/QSD is based on various comments and sources.It uses the devices proposed originally. The CPLD will be used to generate quadrature signals from the DDS. No preamp/filters have been included at this stage.

QSE QSE.gif The QSE circuit is basically the reverse of the receiver with a low level power amp

Note there is no DDS clock circuit at this point. This is still under development, though a simple crystal oscillator module will be used for prototypes.