[Xylo-SDR] A/D interface thoughts

["Phil Harman" <pvharman@arach.net.au>]

Some thoughts on the  Xylo to A/D converter interface (Wolfson or TI).

If  we assume that we want to run the A/D at 192kps with 24 bit samples then 
the BCLK coming from the A/D will be at

192,000 x 64 = 12.288MHz.

Since the LRCLK and data is synchronous with this clock then it seem to me 
that we need to feed the 24.576MHz clock into the FPGA and run a state 
machine from it.

We also need to indicate to the PC program which sample we are sending, left 
or right.
I previously suggested that we use

<0x000000>< left data><right data><0x000000><left data><right data> etc

so that the all zero state is used as a unique flag. As others have pointed 
out since the USB bulk transport scheme assures that the data is received we 
don't need to send the flag that often - perhaps just every time we switch 
to Rx and say every 500 packets.

Also its not a good idea to  use zero  for the flag since the data from the 
A/D is in 2's complement format and zero will occur naturally quite often in 
the data. My suggestion is that we use either the max or min value from the 
A/D e.g.

01111111111111111111111 or 10000000000000000000000

I suggest we use the latter.

Since we have 32 BCLK pulses  available for each channel but only 24 have 
audio data associated then there seems to be plenty of space in which we can 
inset these 3 bytes. If we use Right Justified Audio then the flag could be 
sent immediately after the positive edge of the LRCLK - or after the right 
data if we use Left Justified data.

I suggest we use Right Justified audio.

Any comments, corrections or suggestions?

73's  Phil... VK6APH



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