[Xylo-SDR] FW: Your FPGA Code

["Jeff Anderson" <jca1955@sbcglobal.net>]

Forgot to cc: the list!

-----Original Message-----
From: Jeff Anderson [mailto:jca1955@sbcglobal.net]
Sent: Monday, December 12, 2005 5:15 AM
To: Phil Harman
Subject: RE: Your FPGA Code


Hi Phil,

1.  If you try to define a delay within the Verilog, I think the Quartus
tool, upon compilation, will "optimize" it to 0, and so the circuit may not
work.  But let me ask one of the Altera apps engineers today, and I'll get
back to you.  (Note - you could also insert the delay external to the fpga
by using another IO pin).

How complex of a state machine are you anticipating?

2.  Regarding the assignment of input clock pins for PLL operation, here's
what the Cyclone Device Handbook says:

(Page 6-6 of the Cyclone Device Handbook)
Pins & Clock Network Connections:
You must drive Cyclone PLLs by the dedicated clock input pins CLK[3..0].
Inverted clocks and internally generated clocks cannot drive the PLL. Table
6?5 shows which dedicated clock pin drives which PLL input clock port.

I don't know which Cyclone Part is on the Xylo board, but let me assume it's
an EP1C3T100.  This part has two clock pins that could be used to drive
internal PLL's (only one PLL in this part).  These pins are:

  CLK0:  Pin 10
  CLK2:  Pin 66

NOTE:  From the handbook it appears to me that, because the EP1C3 only has
one PLL, you can only use CLK0 (pin 10) to drive it.  CLK2 normally drives
the second PLL, which is not in this part.  But you should verify my
statement - I just glanced at the data sheet.

(By the way, for reference - the PLL's within the Cyclone & Cyclone II parts
are useful for boosting clock frequencies, but not much more than that.  I
had wanted to use one of their PLL's to recover clock from an 8b/10b-encoded
data stream, but, because of the PLL's limited "input jitter" spec, their
apps engineers advised me not to).

3.  Good question!  Usually, I'm running functional simulations on
submodules (that is, no pins assigned, etc.) and so I compile using only the
"synthesis & analysis" button (the middle purple button, rather than the
left-hand button).  In these cases Quartus always gives me an error if I try
to run the simulator in Timing Mode, so, out of habit, I always run it in
functional mode.  But if you can run timing w/o an error message - go for
it!

73,

- Jeff

-----Original Message-----
From: Phil Harman [mailto:pvharman@arach.net.au]
Sent: Sunday, December 11, 2005 10:13 PM
To: Jeff Anderson
Cc: Xylo-SDR Discussion
Subject: Re: Your FPGA Code


Jeff,

This is simply great - I've been reading all the Verilog tutorials I can
find and non of your tips came up in any of them.  I am sure that many of us
newbies appreciate the effort that you went to in making these suggestions.

I'm making very good progress with the full implementation of the Wolfson
interface and will have it ready for critique very shortly.

Just a few  questions:

 I will need to use the 24.576MHz clock from the Wolfson/TI A/D as the means
of changing states.   It would be useful to frequency double this to allow
me to add more states in the future if needed.  I could use the PLL to do
this but would rather keep this free for something more exciting in the
future. If I were doing this in hardware I would simply use an XOR and delay
the clock to one input, is it this approach sound in an FPGA?

Phil C advised that I need to attach the 24.576MHz clock to pin 66 of the
Xylo FPGA - why can't I use just any pin?

When running a simulation I can choose either Functional or Timing. Until
you pointed out the Functional option I've been using Timing mode which
allows me to generate the simulation waveforms by simply clicking on the
Blue Squarewave button.  What are the reasons for the two modes and when
should each be used?

Thanks in advance for your help.

73's  Phil...VK6APH



--
No virus found in this outgoing message.
Checked by AVG Free Edition.
Version: 7.1.371 / Virus Database: 267.13.13/197 - Release Date: 9/12/2005