Phil
Hey! You think you could port your plans for your HPSDR objective number
three to a "2x4" to the cyclone II that Leon is designing? Sorry to
publish
your PM, but hey, neat stuff, and now we gotta GROUP, which offloads
sections of the entire project!
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Phil Covington said in a PM:
3. I have samples of the new Analog Devices AD9446 16 bit 100 MSPS A/D
convertor. I was working with various QSD designs (trying to improve the
performance at 18+ MHz), but I have come to the conclusion that this is
becoming a waste of time with the new 16 bit high speed converters coming
out. I think I am going to change the design of the HPSDR to use this 16
bit 100 MSPS A/D instead of a QSD based design.
I will use the Xilinx FPGA to act as a DDC (direct digital down
converter -
see AD6620). So basically the RX chain will consist of a
AD9446 A/D and a Xilinx FPGA! Can't get much simpler than that... By
using
a DDC I can increase the dynamic range of the high speed 16 bit A/D by as
much as 26 dB which will put it at a level of performance
that is superior to the QSD - 24 Bit Audio A/D designs. The AD9446
costs about $80 in single unit quantities but it does not need a QSD, does
not need a DDS, and requires less board real estate, so the cost is about
the same in the end. Running the AD9446 at 100 MHz sample rate will allow
you to digitize from 0 to 30 Mhz. The DDC will down sample this 30 MHz
swath of spectrum to something the PC can handle over USB 2.0.