Re: [Xylo-SDR] FPGA pin names in schematic - Some thoughts...

[Philip Covington <p.covington@gmail.com>]

Hi Lyle,

On 1/20/06, Lyle Johnson <kk7p@wavecable.com> wrote:
> > 1. We have a BUS/USB COMMs board to handle communications over the bus
> > and to/from USB.  The main function of this board is to control the
> > bus and handle communications over the bus.  This would be a Cyclone
> > II - Cypress FX2 based board like what Leon is designing.  It could
> > take on other roles as LE space permits.
>
> Do you really need much more than the Cypress USB chip for this?  What
> role does the FPGA play?

The FPGA would route the USB data to/from the plug-in boards based on
some kind of command encoding over the USB comms.  Though, the FX2
does have the GPIF mode which could be used to define a bus I guess. 
Since all of the high speed data to/from USB is though the FIFO
interface (the FX2 steps out of the way) we would need something to
control manage the bus besides the FX2.  The other thing I was
thinking is that by using the FPGA we can redefine the pin meanings on
the backplane.  It would be hard to do this with the FX2 (even the 128
pin part).

> > 2. Since the Cyclone II can do LVDS, maybe we should be looking at
> > having only LVDS signals on the motherboard bus.  This would require
> > that we either use a LVDS capable FPGA/CPLD or a LVDS
> > serializer/deserializer chip on each plug in board to talk to this
> > bus.
>
> I suggest that you have some group of backplane pins labeled
> "user1..userx" so you don't restrict things to only LVDS.  Alternately,
> just have a group of perhaps 8 signal pairs defined as LVDS.
>
> You might have some slower signals running around like I2C, SPI, CAN,
> JTAG (please to consider the ability to use a JTAG chain across the
> backplane), some open collector lines for a wire-ored way to send
> interrupt requests around, etc. By limiting the board to only 100mm
> square, you are ensuring that most systems will be comprised of multiple
> boards.  No one has articulated what is being designed yet -- just some
> flexible hardware for fun.  That being the case, you probably want to
> leave your options open.
>
> Stirring the pot,
>
> Lyle KK7P

It seems like it should be possible to redefine the LVDS pairs on the
bus to single ended LVCMOS depending on what you want to do.  I like
the idea of having the JTAG chain across the backplane.  I would think
that instead of defining certain pins on the backplane to be SPI, I2C,
etc... this could be defined by the FPGA on an application specific
basis.

73 de Phil N8VB