1) Each board must be addressable from the Janus board via I2C or maybe
JTAG in order for the Janus to do the firmware download to each FPGA.
I think the motherboard/bus should directly and distinctly support JTAG,
in which some signals are in parallel, some are daisy-chained. There
may well be a mix of JTAG devices, not only FPGAs, on the various boards
-- including daughter boards.
I feel it is best to have individual JTAG connectors on the boards, JTAG
doesn't usually work with a mix of devices on the chain.
If the motherboard bus supports chaining the JTAG signal, the individual
board can always ignore those bus lines and use a separate connector
(e.g., for a TI DSP or OKI ARM7 CPU). But, if one puts another Altera
Cylcone II on a different board (e.g., the digital downconverter for the
100 MHz 16-bit ADC), it should chain OK from the one on Lionheart.