Re: [Xylo-SDR] Fundamental Atlas design decisions

["Philip Covington" <p.covington@gmail.com>]

Hi Ray,

Warning:  I haven't finished my coffee yet this morning...

I think the quantity 4 plug-in boards for the Atlas was originally the
result looking at using an extruded case that we then dropped.   We
also had discussions of using the Aria case (which has 4 PCI slots on
the back).  I am not sure that four slots will be enough.  I would
like to see 6.  I am at work so I can't look at my Aria case - I am
not sure if there is room for a backplane with 6 slots - Can someone
check this?  The spacing of the boards was dictated by the PCI card
spacing.  If people are not going to use the Aria case then there is
no point letting it dictate the quantity of plug-in boards per
backplane. I also think that if we has 6 slots on the backplane we
could then drop the idea of expansion connectors on the backplane. 
For special cases the plug-in boards could have a daughterboard header
allowing expansion as needed and special functions.

I like the stack-up that you mentioned if we are going to do a 4 layer
board with LVDS in the backplane.  In that case, I'd like to see 4
'lanes' or 'channels' of LVDS in the backplane.  I think the a max
clock speed spec of 200-250 MHz on the LVDS would be adequate.  With 4
 'lanes' we could have up to four high speed clocks between boards.

If we decide to not put LVDS on the backplane then I think we could
get by with a two layer board - top would be ground plane and bottom
would be signals/power.  That way we at least have a ground plane
between the bus and the plug-in boards for shielding.  Two layers
would be cheaper to make than 4 - it depends on how much we think we
need LVDS.

The bus needs to be generic enough to support other projects besides
Janus and the FPGA-USB board.  Lyle's suggestion of daisy-chaining a
few of the signal lines between boards is a good one.

73 de Phil C







On 2/21/06, Ray Anderson <ray.anderson@xilinx.com> wrote:
> A few thoughts regarding the Atlas design:
>
> 1) Here is one possible stackup which keeps the LVDS signal on a
> separate layer from the other signals  (audio, clock, JTAG, I2C, other
> TTL/CMOS signals/control, etc.). I'm showing the PWR layer on the
> outside, but it could be swapped with the GND layer. Having GND on the
> outside may be a bit better from a safety/shorting/EMI perspective, but
> having it between the LVDS and signal layer is probably better from a SI
> perspective since the reference path for the clock and others won't be
> as dependent on the goodness of the decoupling.
>
>
> -------------------------  PWR
>
>
> -------------------------  LVDS (100 ohm differential)
>
>
> -------------------------  GND
>
>
> -------------------------  Other Signals
>
>
> 2) We need to decide on a substrate thickness for the stackup. If we go
> for a total typical thickness of .062 (which will provide good
> mechanical rigidity for the backplane) then the dielectric layers will
> be about 18 mils which is reasonable. This decision will dictate the
> width and spacing of the LVDS conductors that need to have a 100 ohm
> differential impedance.
>
>
> 3) Designers of the Janus and Lionheart boards should endeavor to keep
> the LVDS driver/receivers as close as possible to the connector as
> possible in order to minimize stub lengths (important in a point to
> multipoint system).
>
>
> 4) We'll need to optimize the signal to ground ratio for the LVDS
> connector pinout to minimize SSO problems.
>
>
> 5) Backplane decoupling is important as is buss termination. If the
> design were to only support Lionheart and Janus then termination would
> only be required on those boards and the backplane would be
> 'transparent'. However since we will have a minimum of 4 slots then
> backplane termination is required. If the add on 'buss extenders' as
> envisioned by Eric materialize we will need to make provisions to
> turn-off the backplane termination scheme and move it out to the
> extenders.
>
>
> There are lots of other issues to be dealt with, but these are some
> basic but important ones that will effect the viability of the whole
> design.
>
>
> Ray   WB6TPU

>