Helios Small Transmitting Loop Antenna and Controller
This project describes a small transmitting loop antenna and controller/motor/tuning capacitor combination that connects to the Atlas backplane and automagically keeps a loop antenna in tune as you change the frequency of any HPSDR.
Please note that this project is a “WORK IN PROGRESS” and not intended to be taken as a fully-operational, well-documented fully-tested product. Currently, the prototype is operational, and I am confident that anyone who wishes to duplicate a similar project can be successful, but as yet, all the T’s are not crossed nor are the I’s dotted. Hopefully that will all happen in a timely manner, but until then, please don’t expect all the information here, and especially the code, to be either complete or of rigorously professional quality. If you can’t find the information here that you want, please email me and I’ll do everything I can to provide it. Also please note that as a work in progress, I welcome, and even solicit, your ideas, suggestions, and comments (and maybe even some criticism!). Any errors or mistakes herein are mine and mine alone. (Mea culpa, in advance.) Please let me know about them and I’ll correct them ASAP. Contact me at firstname.lastname@example.org
Helios was the Sun god, of course, and the name means radiant or shining. We certainly hope that this antenna radiates! Also, it is the root for helical, which means “in the shape of a coil”; which fits fairly well too. So Helios it is.
In these days of antenna restrictions, there has been much discussion of small, easily transported, and discretely deployed hf antennas. One of these antennas is the small transmitting loop, which most generally consists of copper tubing formed in a loop with diameters ranging from less than a foot (for vhf use) to large structures intended for 80 and 160 meters. The loop circumference can be less than 1/10 wavelength and the loop is brought to resonance with a capacitor across the endpoint of the loop. Efficiencies can run very high, even into the 90 percent range, and the antenna seems to operate quite well even close to the ground. The loop, however, exhibits extremely high Q, and bandwidths can be in the low tens of kilohertz. This necessitates constantly retuning the antenna capacitor to resonate the desired operating frequency.
The controller described here reads frequency information from the Atlas backplane in I2S format and converts the frequency data into an index into a lookup table in a PIC processor. The lookup table then provides a pre-programmed capacitor position to a motor driver that positions the capacitor at the proper location to resonate the antenna.
There is a plethora of information on small transmitting loops in the ARRL Antenna Book as well as numerous sites on the web. A couple of the most comprehensive are W2BRI’s site () and AA5TBs site (). The DX Zone has a list of exhaustive links as well: (). Be sure to note the design spreadsheet on AA5TBs site, which is an invaluable design tool. At least one loop is available commercially from MFJ, although it is pricey and it doesn’t control from receiver frequency, but is tuned for minimum SWR.
A typical design which has been built as a prototype is described by Robert Capon in “You Can Build: A Compact Loop Antenna for 30 through 12 Meters”. This article is available from the QST archives on the ARRL website. It’s a very simply constructed 3-foot diameter loop using 5/8-inch copper plumbing tubing and resonated with a capacitor. The prototype for this project has been built using this article as a guide. It should be noted, however, that any loop antenna, so matter what size or configuration, can be tuned using this controller. In fact, any antenna tuner that can be tuned from a rotating shaft or any antenna that can be tuned using a variable capacitor or variable inductor can be used as well.
The controller is designed on a 2.5 by 3.75-inch PWB and can either be plugged directly into the Atlas backplane, or alternately mounted away from the backplane and connected to the Atlas by three signal wires and a ground. The controller can be powered from the Atlas backplane or alternatively, powered from an on-board 5-volt regulator. The power can then be supplied by a wall wart delivering anywhere between 8 and 20 volts ac or dc. There are five switches and six indicator lights that operate the controller. These switches can be mounted on the PWB or can be located off-board. Dual footprints are provided for either miniature screw terminals or headers. Motor voltage, being significantly higher than used by the board electronics, is connected separately. The board has two RJ-45 type jacks; one for an eight-wire CAT5 or CAT6 cable that is used to power the stepper motor; the second is for a four-wire telephone cord that brings the position pot signals to the board. A six-pin header connects to an in-circuit programmer to initially program the PIC. There are a number of spare inputs for experimentation and expansion. The controller takes digital signals corresponding to the SDR DDS frequency and positions the antenna tuning capacitor so that it resonates the antenna at, or very near, to this frequency. As the frequency of the SDR is changed over the range of the antenna, the antenna tuning motor/controller will keep the antenna at resonance. Since the antenna exhibits the same high Q performance while receiving as during transmitting, the antenna needs to be tuned for reception as well. Note that this controller will also be able to be adapted to many types of motor-driven local or remote antenna tuners to offer the same “always tuned” performance.
The heart of the controller is a PIC 18F4321 processor, which are normally available from Mouser and other suppliers for about $5.00 ea. Microchip has an extensive website and tons of free software as well as a free IDE. The 18F4321 is used since it has internal communication ports, A/D converters, and PWM motor controllers. If using the PWB developed for this project, you will need a programmer capable of programming the 18F4321 through the in-circuit port, and use the free IDE from Microchip. These programmers are available on Ebay starting at around $30.
On the Atlas backplane, there is a bit stream in I2S format that contains, among other things, 32-bit binary-format frequency information. This frequency information is decoded to derive an index into a lookup table implemented in the PIC. The output of the lookup table is the number of steps (from an index) that the motor must turn to arrive at the resonant point of the antenna corresponding to the input frequency.
A routine is provided to calibrate the controller for each tuning point of the antenna. To calibrate a particular frequency, the transmitter is set to “TUNE” at a particular frequency and a forward or reverse button on the controller is pressed to tune the antenna for lowest SWR. Once reached, the calibrate button is pressed to record the position in the lookup table. For positions outside the band, an antenna analyzer can read the swr or the controller can be calibrated from maximum received signal strength.
The controller also contains a TI INA125P precision instrumentation amplifier that amplifies the output of a bridge circuit. One leg of the bridge is the potentiometer that follows the position of the capacitor shaft. This position potentiometer is used to accurately locate the index position at minimum usable capacitance. All frequencies are then calibrated as a number of steps of the stepper motor from this index position. When the controller is first powered, or reset, the motor locates and resets to this index position, then, if the receiver is in operation, immediately tunes to the operating frequency.
Almost any five- or six wire unipolar stepper motor that can develop sufficient torque to operate the selected capacitor can be used. (Bipolar stepper motors can be used, but would necessitate minor wiring changes on the PWB as well as code changes. Dc motors would require significant code changes as well as wiring changes and won’t be detailed here.) Ebay is a great source for these types of steppers at reasonable prices. Voltage ratings are generally not as important as a stepper can be driven with significantly higher or lower voltage than rated as long as the current is limited.
On the prototype, a 1.8 degree/step stepper motor is directly coupled to a ¼ inch insulated shaft (remember that the cap has about 5KV on it at resonance!) that is coupled to a 22-turn vacuum capacitor. On the ¼ inch shaft is a sprocket that drives a short timing belt. This couples the shaft to a 10-turn position potentiometer with an overall turns ratio of 2.2:1. Thus, 22 turns on the capacitor shaft equals 10 turns of the pot. This pot position provides the “index” point at one end of the capacitor travel from which all other positions are derived.
The voltage fed to the stepper motor is adjusted to provide enough torque to operate the capacitor shaft, but not much more. Should a malfunction cause the motor to overdrive the limits of the capacitor, the motor simply stalls without damaging the cap.
The tuning capacitor must withstand a considerable amount of high voltage, necessitating either a big “bread slicer” transmitting cap or, preferably, a vacuum cap. Voltages of 4 or 5 kV are typical at 100 watts; and past 15kV at 1000 watts. Tuning ranges go from 5pf up to several hundreds of pf. For the compact loop described above, and at 100 watts, a capacitor that tunes from 5pf up to 100 pf. provides a tuning range roughly between 10mHz and 30mHz. If a mechanical “bread slicer” is used, a two section cap is generally preferable since the each of the ends of the loop can be connected to each stator and the rotor rotates between them. This keeps the overall loop resistance low, since the loop connections do not have to be made through the rotor wipers. MAX-GAIN systems, at  is a good source for surplus vacuum capacitors. Ebay is also a fertile ground for searching for a suitable cap. There are several Ukrainian sources at bargain prices, but shipping times can run several months, and shipping damage has been reported with these as well.
If you opt for a “bread slicer”, note that the entire range is covered in only ½ turn of the shaft. I have not experimented with these, but I would imagine that you would need a gearbox in front of the cap to provide sufficient resolution. Indexing would be simplified, however, since you could merely stall the motor against the stops to index the shaft.
It might be noted here that the typical vacuum cap has about 22 turns end to end; with a stepper motor that has a 1.8 degree/step increment, this results in 200 steps for one motor shaft rotation. To turn the cap its full range then requires 4400 steps. The PIC, however, only has enough memory for about 2000 steps. In order to encompass the full range of the cap, the motor actually double-steps for each single position increase. In preliminary testing, this resolution seems to be quite adequate for operation while keeping the SWR very low. If one needed higher resolution, it would be fairly easy to recode over a smaller frequency range.
There are several databases on the HamSDR website in the Public Download directory and “Loop Antenna” folder.  Currently, you can find the code, the BOM and the CAD files. The CAD files use proprietary applications that you can download from ExpressPCB  website for free. For convenience, I used ExpressPCB for the prototypes, and you can view the schematics as well as the current board layout using these tools. For higher volumes, we need gerber files and we are now in progress of using Eagle schematic and layout applications to generate these files. As they become available, I will update the database with these files. Please note that the board described in the files has just arrived and will be checked out very soon. Hopefully, no changes will have to be made, but at this point it is not certain. Note also that resistor values in the bridge circuit will almost certainly have to be modified.
The code needs more documentation, of course. (Doesn’t it always?) I am certainly not an expert at PIC programming, and I would imagine that an accomplished coder would laugh at my code, but it works so I offer it freely and will be making improvements in the future as well as making progress in further documentation.
At first, the processor is initialized and constant names are defined, and interrupts vectors are stated. The first section of the operational code decodes the I2S bus frequency data. You can find descriptions of the I2S bus on the web; it stands for Inter-Integrated circuit-Sound format.
Here is a description from Phil Harman of the I2S bus data on the Atlas Backplane:
Command and control data is broadcast over the Atlas bus (C20) for use by other cards e.g. Mercury and Penelope. The data is in I2S format with the clock being CBLCK and the start of each frame being indicated using the negative edge of CLRCLK.
The data format is as follows: <PTT><[47:44]address><[43:12]frequency><[11:8]band><[7:1]OC><mode> for a total of 49 bits. Frequency is in Hz and 32 bit binary format and OC is the open collector data on Penelope.
Phil further reports that the signals on the Atlas bus are correct in SVN under ..../Altas/Atlas to Janus V2-OzyV2-Penelope Interface.xls –
Using this information, the code programs the USART to receive the clock and data as well as the start frame signal. Note that once received by the UART, each data byte is in wrong order and has to be flipped end for end.
The code grabs the frequency information and shifts it and subtracts from it to provide a zero index at the lowest frequency in use. The offset in the code is then added to bring the address to the first location in the lookup table. Increasing frequency moves upward in the table.
**More to follow**
--Ken 18:41, 30 September 2007 (PDT)
FPGA Programming: Verilog & VHDL
Which is best? Verilog or VHDL?
The question was asked recently on our HPSDR Discussion List about Verilog versus VHDL and which was more user friendly. In response to this query, Rick Eversole, N6RNO, gave this reply:
(Reprinted here by permission of the author)
Yet another answer from one who has used both languages for 17 years. I have worked for Cadence, Mentor Graphics and now Synopsys. I get paid to know both languages. I have written thousands of lines of code in both. I know 29 programming languages (including Verilog and VHDL). I prefer Verilog and in recent years it appears that VHDL is finally falling behind.
While Verilog is being upgraded to "SystemVerilog", the VHDL camp is finding it hard to find funding to update the latest LRM. "SystemVHDL" may not actually be needed but as it stands now I do not think it will ever happen.
Verilog is C-like (Prahbu Goel and Phil Morby [creators of the language] liked C). Not strongly typed. Subject to coded race conditions. But fastest to learn and tuned toward hardware better than VHDL. Verilog simulates faster than VHDL. Verilog has gate level primitives (AND, NAND, NOR etc) as part of the language. A useful value type system is part of base Verilog.
VHDL is based upon ADA (Many of the same people who specified the ADA language were involved in the creation of VHDL). It is a strongly typed language. It is very hard to code a race condition. It takes longer to learn. More typing is involved to accomplish the same task in VHDL as compared to Verilog. VHDL simulates slower than Verilog (2-4x slower is typical even for gate level simulations). VHDL does not have gate primitives. You have to code them in RTL style.
The "VITAL" specification provides a set of gate primitves that map to Verilog primitives. VHDL does not have a logic system that is useful for gate designs. You need the "standard logic 1164" package which ships with any real VHDL simulator. Like Vital this is a layer on top of the base language.
Over the years I have seen side by side test with "expert" VHDL users and Verilog users. In general the Verilog users out perform the VHDL users. There are lots of issues with how these tests are constructed but my experience shows that Verilog is fasest to get the design done but VHDL designs often are easier to maintain and update.
Each language has advantages. The new SystemVerilog language will remove all but VHDL's strong typed "advantage". Whether strongly typed is a real advantage is a debate for another time.
In practice, it is not possible to translate between the languages. Semantics are incompatible. You have to completely recode in a non-mechanical process. Translators can help but 30% recode is not uncommon. (unless you have pure structural code then translation can be almost 100%).
--Rick "The Rhino" N6RNO
Example Verilog Code from Phil Covington N8VB: http://www.philcovington.com/FPGA/
Example Verilog Code from Bill Tracey KD5TFD: http://www.tracey.org/wjt/sdr1k/Xylo/9850Control.zip
Verilog Tutorials and Resources:
Good Reading Link
GNU Radio has a nice page with a lot of good reference reading information on it. http://gnuradio.org/trac/wiki/SuggestedReading
Here's a link to one possible VERY SMALL power supply for the Atlas backplane: http://www.mini-box.com/s.nl/it.A/id.417/.f?sc=8&category=13
Please note that extensive testing has not been performed yet on this unit and as of this writing it is not in stock. The HPSDR group does not necessarily recommend this particular supply at this time.
HF Power Amplifiers
HFPROJECTS.com, operated by Virgil K5OOR, offers some interesting kits which might be suitable for HPSDR project transmitting when Phoenix or Penelope becomes available, or for other transmitters. The link is http://www.hfprojects.com/newsletter.htm Two current offerings are a "pre-amp" (PA-100) for boosting a HF signal from the 100 mw range to the 5 watt or greater region, to be able to drive the SUPERPACKER PRO solid state amplifier -- a 100 watt continuous duty beast! Be aware that this is NOT an open source project, and the one submitting this information has some serious reservations about the operation of the amplifier and the project.
A Novel Grounded Base Oscillator Design for VHF/UHF Frequencies
This is a PDF file submitted by Ulrich Rohde, N1UL, which can be downloaded (about 3 MBytes) from http://hpsdr.org/downloads/GBPhaseNoiseAnalysis4-20-07.pdf
MODIFIED NORTON AMP
Submitted by Ulrich Rohde, N1UL:
This simulation using the Infineon BFP490 agrees with my test-circuit within about 0.2dB. Depending on the transformer, (2+2)/2, inductance, this works from 1 MHZ to 1 GHz max. The IP3 of about 38 dBm is excellent, the NF about 2dB. The reverse isolation can be more then 60dB, and a push-pull version has reduced IP2.
Click on the "media" link below each drawing if you want a PDF file with slightly higher resolution.