Difference between revisions of "METIS"
| Line 14: | Line 14: | ||
[[Image:OzyII_Block_Diagram_V1.4.jpg|thumb|600px|Current block diagram for OzyII. 26 September 2009]] | [[Image:OzyII_Block_Diagram_V1.4.jpg|thumb|600px|Current block diagram for OzyII. 26 September 2009]] | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
By using a large FPGA if offers the potential to add a soft core microprocessor in the future so that the board can run a full TCP/IP stack, UDP etc. e.g. uIP http://www.sics.se/~adam/uip/index.php/Main_Page | By using a large FPGA if offers the potential to add a soft core microprocessor in the future so that the board can run a full TCP/IP stack, UDP etc. e.g. uIP http://www.sics.se/~adam/uip/index.php/Main_Page | ||
| Line 52: | Line 26: | ||
In general, an Ethernet subsystem is divided into two parts: the media access controller (MAC) and the physical device (PHY or line interface). Generally, the MAC handles generating and parsing physical frames and the PHY handles how this data is actually moved to or from the wire. The PHY is just a means of transmitting raw bits rather than logical data packets over a physical link that are connecting network nodes. | In general, an Ethernet subsystem is divided into two parts: the media access controller (MAC) and the physical device (PHY or line interface). Generally, the MAC handles generating and parsing physical frames and the PHY handles how this data is actually moved to or from the wire. The PHY is just a means of transmitting raw bits rather than logical data packets over a physical link that are connecting network nodes. | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
Useful info: | Useful info: | ||
Revision as of 03:40, 26 September 2009
OzyII (or maybe Aussie II?) will be a high speed PC interface. Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.
Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.
Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.
User input relating to the design and features is requested via the HPSDR reflector.
Project Leader: Phil, VK6APH
17 July 2009
By using a large FPGA if offers the potential to add a soft core microprocessor in the future so that the board can run a full TCP/IP stack, UDP etc. e.g. uIP http://www.sics.se/~adam/uip/index.php/Main_Page
Initially we will use the Gigabit PHY as just a fast connection to the PC and use raw frames to communicate.
Feedback and comments are requested via the HPSDR reflector.
Ethernet Notes:
In general, an Ethernet subsystem is divided into two parts: the media access controller (MAC) and the physical device (PHY or line interface). Generally, the MAC handles generating and parsing physical frames and the PHY handles how this data is actually moved to or from the wire. The PHY is just a means of transmitting raw bits rather than logical data packets over a physical link that are connecting network nodes.
Useful info:
http://www.techonline.com/article/pdf/showPDFinIE.jhtml?id=2088017281
http://www.cs.rice.edu/CS/Architecture/docs/shafer-tree0611.pdf
Altera White paper on Ethernet using Cyclone III and NIOS soft core
http://cm.altera.com/g/?QYKFH2NRLY:SU6QAW3Y1V=ssID:480603690
