Difference between revisions of "METIS"

Revision as of 00:59, 29 June 2009

OzyII (or maybe Aussie II?) will be a high speed PC interface. Whilst the original Ozy board has served us well to date, in order to implement some of the future HPSDR projects we are going to need a faster interface between the various boards on the Atlas bus and the PC.

Aussie II is a kick off point for this project. Since this board will not need to support the SDR1000 there will be room for testing other high performance/speed interfaces.

Initial thoughts are around an Atlas size board that contains a large, leaded, Altera Cyclone III FPGA connected to a Gigabit Ethernet PHY.

User input relating to the design and features is requested via the HPSDR reflector.

Project Leader: TBA

Ethernet Notes:

In general, an Ethernet subsystem is divided into two parts: the media access controller (MAC) and the physical device (PHY or line interface). Generally, the MAC handles generating and parsing physical frames and the PHY handles how this data is actually moved to or from the wire. The PHY is just a means of transmitting raw bits rather than logical data packets over a physical link that are connecting network nodes.

Possible PHY devices ( non BGA or PCI interface, NDA not required)

National DP83865 development kit - http://www.morethanip.com/boards_10_100_1000_dp83865.htm 500EUR + 100EUR postage

reference design - http://www.national.com/appinfo/networks/files/dp83865_refdesign.pdf

http://www.national.com/analog/interface/refdesign_demoboards - for Orcad files

Useful info:

http://www.wireshark.org/