OZY REVA STARTUP

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Revision as of 12:50, 14 February 2007 by WikiSysop (Talk | contribs) (New page: ==Start Up Notes For OZY REVA Alpha Boards== 07052006-1: [Issue] Pin 5 on resistor pack R16 is tied to +3.3VBUS. Is should be tied to +3.3VD. Since Pin 5 and Pin 10 of R16 are common, thi...)

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Start Up Notes For OZY REVA Alpha Boards

07052006-1: [Issue] Pin 5 on resistor pack R16 is tied to +3.3VBUS. Is should be tied to +3.3VD. Since Pin 5 and Pin 10 of R16 are common, this effectively connects +3.3VD and +3.3VBUS together. The trace leading to Pin 5 of R16 should be cut. Pin 5 does not need to be connected to anything since Pin 5 and Pin 10 are common and Pin 10 is correctly connected to +3.3VD.

07052006-2: [Issue] Pin 35 (EA) of U5 (CY7C68013A FX2) was left floating. Pin 35 (EA) when low selectes internal memory access and when high selects external memory access on the FX2. Pin 35 (EA) must be jumpered to ground (low) to ensure that the FX2 properly enumerates on USB. A small "U" jumper can be placed between Pin 35 (EA) and Pin 33 (RESERVED) to accomplish the fix.

07052006-3: [Issue] Pin 101 (WAKEUP) of U5 (CY7C68013A FX2) was left floating. Pin 101 (WAKEUP) is an input to wake up the FX2 from a suspend state. Pin 101 (WAKEUP) should be pulled high for proper operation.

07052006-4: [Info] Suggested initial jumper settings

-Two Pad Jumpers-

J10 - leave open

J11 - leave open

J12 - leave open

J13 - leave open

J25, J30 - make jumper

J27, J28 - only make if you want to put the I2C from the FX2 on to the Atlas bus

J29 - leave open for now? Nothing out there on the Atlas bus to reset yet?

-Three Pad Jumpers-

J9, J16, J18, J19 selects whether pins 1 through 4 of J8 (DB9F) are routed through the ULN2003A or not. In position 1-2 the ULN2003A is bypassed. Jumper 1-2 for initial testing.

J22 selects whether the common input of the ULN2003A is connected to +3.3VD or an external voltage supplied on pin 9 of J8 (DB9F). Jumper 1-3, which will select the externally supplied voltage.

J14, J15 - Make pins 1-2 for initial testing.

J26 - Make 1-3 unless you want to use the +3.3VBUS supply from the Atlas instead of the locally regulated +3.3VD

07062006-1: [Info] To power the OZY from the USB supplied +5V you can jumper the USBV+ pad (near the USB connector) to Pin A32 or Pin C32 of the DIN41612 96 pin connector. You might want to monitor the current draw on this supply each time you make a change to the FPGA code to make sure you are not exceeding 100 mA.

07072006-1: [Warning] When compiling a program for the FPGA in Quartus II, make sure that you set all unused pins to inputs. This can be accomplished by going to Assignments->Device in the Quartus II menu. Select Device in the Category window if not already selected. Click on the "Device & Pin Options..." button. The "Device & Pin Options" dialog will open. Select the "Unused Pins" tab and set "Reserve all unused pins:" to "As input tri-stated". Quartus II defaults to setting all unused pins as outputs driving ground. {Does anyone know how to change it to default to inputs? - N8VB}

07072006-2: [Info] IC U2 (DS2480B) and diode D2 were not shipped with the parts kit for the OZY alpha boards. The DS2480B is on backorder from Digikey with an estimated ship date of 07/07/2006. Diode D2 was left out of the parts list and was not ordered. It is a 0805 SMT schottky diode that protects the +3.3VD supply on OZY from externally supplied voltages on pin 1 of J17 - the logic analyzer/IO expansion header. {I do not plan on ordering this diode for the alpha boards - N8VB}

07122006-1: [Info] To test out the FX2 on OZY there is a firmware hex file in HPSDR SVN: OZYV1FW.hex. It can be downloaded with the Cypress EZ-USB utility and soon our own utility using libUSB.

07162006-1: [Info] The green indications on the LEDs are the ANODE. These go towards the small "a" on the boards. "a" means ANODE - it is not an "o"!!!

07172006-1: [Info] A modified inf file can be download from http://www.philcovington.com/HPSDR/Cypress/ which includes entries for the HPSDR VID and PID for use with the Cypress driver.

07172006-2: [Info] An inf file for libUSB-Win32 can be downloaded from http://www.philcovington.com/HPSDR/libUSB/ which includes entries for the HPSDR VID/PID for use with the libUSB driver.

07172006-3: [Info] Soon I will add a link to installation instructions on getting OZY to work with the libUSB driver.

07202006-1: [Info] See http://www.philcovington.com/HPSDR/OZY/UTILS/ for documentation on setting up libUSB and the OZY utilities.

07212006-1: [Issue] The nSTATUS pin from the FPGA (Pin 121) needs to be pulled up to +3.3VD by a 10k resistor. The 10k resistor was left out on the alpha boards and can cause problems with downloading the FPGA.

07212006-2: [Info] The INIT_DONE output pin of the FPGA is connected to LED D12. To enable the INIT_DONE output you need to go to the Assignments->Device menu in Quartus II and click the Device & Pins Options button. On the General tab you have to checkmark "Enable INIT_DONE output". If you recompile the project and download it to the FPGA you will see that D12 illuminates while the FPGA is being programmed. When programming is done the LED D12 turns off.