Penelope - Trouble Shooting

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Low Power Output - T2 Reversal

On the TAPR production boards transformer T2 was installed 180 degrees from its correct orientation:

Transformer T2 (the white box) in the CORRECT orientation
"Description of Error:
Transformer T2 is rotated 180 degrees from the correct orientation.
Low power output, especially at 6M (~0.25W or 3dB lower than the specified 0.5W). You may not even notice this on the lower frequencies, as 0.5W is achievable on some frequencies even with the transformer installed upside down.
Corrective Action:
Remove T2 and reinstall it 180 degrees from the original orientation.
The T2 orientation dot on the silkscreen is incorrect.
Except for slightly lower power output, this error will not adversely affect transmitter operation."

Investigating low output power

An [email] on the discussion list, stated:

"I am unable to get anything like 0.5W out. With the PA gain set to min (38dB) in PowerSDR and the drive level set to 100. I am only getting 49mW out on the display when I select Tun in PowerSDR."

Several suggestions were made:

  • In PowerSDR the drive level needs to be set all the way to 100, and under SetUp, PA Settings, set all of the PA setting windows to 38.8.
  • The module "from Gerd works according to specifications while TAPR´s Penny gives somewhat less output power due to wrong placement of transformer T2. ... I can confirm the T2 on Gerd´s Penny is turned 180 degrees." "Please note that the slider for drive has two separate settings, namely one for output power when activating PTT or the cw key and one for TUNE. Normally the output power setting for TUNE is set to a lower default value by manufacturers. Please check that the number display of the associated slider for output power really shows 100 when you click on TUNE and move it to 100 while in TUNE mode if it shows less."
  • The gain of the OpAmp output stage is about 23 dB. So for 1/2 Watt out, you need +27 dBm - 23 db or +4 dBm into T1 for full output. Check for about 1 Volt peak to peak at JP2 pin 1 or 2. Look for about 1.2 Volt peak to peak at JP3 pin 1 or 2. If not getting that, then look for problem between there and the DAC.
  • The DAC is currently set to put out a current of about 20 mA, which into a 200 Ohm transformer would produce about 4.4 Volts peak to peak, EXCEPT that the output stage of the DAC hard clips at +/- 1.1 Volts. The power control loop in the FPGA further limits the level to keep the output out of clip. T3 is a 2:1 voltage (4:1 impedance) step down transformer, so results in 600 to 700 mV peak to peak at JP3, with the power/control loop at maximum. Look for DC voltage on the two DAC output lines. They should both be held at 0 Volts by the transformer. If there is any DC voltage, there is a problem with T3, or solder joints.