Difference between revisions of "User:VK2NRA/sandbox2"

From HPSDRwiki
Jump to: navigation, search
(lectures...)
 
(HPSDR Verilog Lectures: start filling from Graham's email)
Line 10: Line 10:
 
!  width="100"|Lecture notes and Labs
 
!  width="100"|Lecture notes and Labs
 
|-
 
|-
|  Lecture 1 title and a short description of content.
+
|  Lecture 1: Verilog as a Hardware Description Language (HDL) Overview, Introduction, Syntax and Rules.
 
|  [http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar *]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_01_20090129.rar *]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar *]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_01_20090129_MP4.rar *]
 
|  [http://verilog.openhpsdr.org/Lab1.rar *]
 
|  [http://verilog.openhpsdr.org/Lab1.rar *]
 
|-
 
|-
|  Lecture 2 title and a short description of content
+
|  Lecture 2: The Verilog Hardware Description Language. Registers, Assignments, Operators, Statements, Functions, Tasks.
 
|  [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]
 
|  [http://verilog.openhpsdr.org/2009-02-02_Verilog_Lecture02.rar 28MB]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_02_1280by720.rar 64MB. Sometimes blocked by chat window, hopefully it's OK.]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
 
|  [http://verilog.openhpsdr.org/VerilogLecture_02_iPhone.rar 53MB iPhone video], [http://verilog.openhpsdr.org/Lab2.rar Labs]
 
|-
 
|-
title
+
Lecture 3: What Good is Verilog? Programming Structure, Concurrent Processes, and The Notion of Time, Blocking Assignments, and The Simulation Process.
 
|
 
|
 
|
 
|

Revision as of 11:37, 9 May 2009

HPSDR Verilog Lectures

by Kirk Weedman KD7IRS

Lecture Title WMV format MP4 format Lecture notes and Labs
Lecture 1: Verilog as a Hardware Description Language (HDL) Overview, Introduction, Syntax and Rules. * * *
Lecture 2: The Verilog Hardware Description Language. Registers, Assignments, Operators, Statements, Functions, Tasks. 28MB 64MB. Sometimes blocked by chat window, hopefully it's OK. 53MB iPhone video, Labs
Lecture 3: What Good is Verilog? Programming Structure, Concurrent Processes, and The Notion of Time, Blocking Assignments, and The Simulation Process.




Lecture 3 - Video in MP4 format, 1280 x 960 resolution, 65MB.

Lab 3 instructions and all labs for Lecture 3

Lecture 4 - Video in MP4 format, 1280 x 960 resolution, 85MB.

[1]Lecture 4 - Video in WMV format, 1280 x 960 resolution, 123MB.

Lab 4 instructions and all labs for Lecture 4

Lecture 5 - Video in MP4 format, 1280 x 960 resolution, 65MB.

[2]Lecture 5 - Video in WMV format, 1280 x 960 resolution, 90MB.

Lab 5 instructions and all labs for Lecture 5

Lecture 6 - Video in MP4 format, 1280 x 960 resolution, 43MB.

Lecture 6 - Video in WMV format, 1280 x 960 resolution, 64MB.

Lab 6 instructions and all labs for Lecture 6

Lecture 7 - Video in WMV format, 1280 x 960 resolution, 32MB. Thanks to Michael Kreeger since I had an audio problem with my recording

Lecture 7 - Having problems trying to convert WMV to MP4. If anyone can do this please let me know.

Lab 7 instructions and all labs for Lecture 7

Lecture 8 - Video in MP4 format, 1280 x 960 resolution, 116MB (1 hr 39min)

[3]Lecture 8 - Video in WMV format, 1280 x 960 resolution, 132MB (1 hr 39min)

Lab 8 instructions and all labs for Lecture 8

OneWire Verilog code as discussed during Lecture 7 & 8 & 9 videos

Lecture 9 - Video in MP4 format, 1280 x 960 resolution, 105MB (1 hr 32min)

Lecture 9 - Video in WMV format, 1280 x 960 resolution, 146MB (1 hr 32min)

Lab 9 instructions and all labs for Lecture 9

Verilog 1995 vs 2001 document - Please read this document so you know about some of the new features of Verilog 2001

Lecture 10 - Video in MP4 format, 1280 x 960 resolution, 75MB (1hr 14min)

Lecture 10 - Video in WMV format, 1280 x 960 resolution, 101MB (1hr 14min)

Lab 10 instructions and all labs for Lecture 10

[4]Here are some reference materials Peter Hughes N7BMG gave me that he downloaded from the internet. I thought these may be of interest.

verilog_2001_ref_guide.pdf

verilog_quikref.pdf

VerilogQuickRef.pdf