Difference between revisions of "Verilog"

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| [http://verilog.openhpsdr.org/Lecture_03_1280by960.rar 65MB]
 
| [http://verilog.openhpsdr.org/Lecture_03_1280by960.rar 65MB]
 
| [http://verilog.openhpsdr.org/Lab3.rar Labs]
 
| [http://verilog.openhpsdr.org/Lab3.rar Labs]
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|-
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| Lecture 4: Non-Blocking Assignments, and much more on Simulation Process
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| [http://verilog.openhpsdr.org/Lecture_04_1280by960_WMV.rar 123MB]
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| [http://verilog.openhpsdr.org/Lecture_04_1280by960_MP4.rar 85MB]
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| [http://verilog.openhpsdr.org/Lab4.rar Labs]
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|-
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| Lecture 5: Digging Deeper, Strengths, Decompositions, I/O Assignments, Time and Time Scales Parameters and Primitives
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| [http://verilog.openhpsdr.org/Lecture_05_1280by960_WMV.rar 90MB]
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| [http://verilog.openhpsdr.org/Lecture_05_1280by960_MP4.rar 65MB]
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| [http://verilog.openhpsdr.org/Lab5.rar Labs]
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|-
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| Lecture 6: Input/Output, Formatting, Monitoring, Files, "disable, fork and join" Statements Proceedural Continuous Assignments.  Dealing with Delays
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| [http://verilog.openhpsdr.org/Lecture_06_1280by960_WMV.rar 64MB]
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| [http://verilog.openhpsdr.org/Lecture_06_1280by960_MP4.rar 43 MB]
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| [http://verilog.openhpsdr.org/Lab6.rar Labs]
 
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The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].
 
The complete list of lectures is available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/].

Revision as of 21:47, 11 May 2009

Verilog is a hardware description language used to model processes in the FPGAs of several HPSDR boards.

A course was presented by Kirk Weedman. It consisted of ten one hour recorded lectures on how to program in Verilog, including tools usage, and another five lectures on code walk-throughs for the code inside of Mercury, Penelope, Ozy, and the signal flows between them. Many lectures have an additional half hour of demonstrations or examples of the programming and simulation tools in the context of the lecture's topics.

Lectures 1 through 10 are about learning to program in Verilog.

Lectures 11 through 16 are special topics, focusing on the Verilog code as used inside of Mercury, Ozy, and Penelope, issues, and improvements being developed by Kirk for communicating between the modules, which all are in separate clock domains.

Lecture Title WMV format MP4 format Lecture notes and Labs
Lecture 1: Verilog as a Hardware Description Language (HDL) Overview, Introduction, Syntax and Rules. * * *
Lecture 2: The Verilog Hardware Description Language. Registers, Assignments, Operators, Statements, Functions, Tasks. 28MB 64MB. Sometimes blocked by chat window, hopefully it's OK. 53MB iPhone video, Labs
Lecture 3: What Good is Verilog? Programming Structure, Concurrent Processes, and The Notion of Time, Blocking Assignments, and The Simulation Process. 65MB Labs
Lecture 4: Non-Blocking Assignments, and much more on Simulation Process 123MB 85MB Labs
Lecture 5: Digging Deeper, Strengths, Decompositions, I/O Assignments, Time and Time Scales Parameters and Primitives 90MB 65MB Labs
Lecture 6: Input/Output, Formatting, Monitoring, Files, "disable, fork and join" Statements Proceedural Continuous Assignments. Dealing with Delays 64MB 43 MB Labs

The complete list of lectures is available at http://verilog.openhpsdr.org/.