Difference between revisions of "Verilog"
From HPSDRwiki
(start verilog page(s)) |
|||
Line 5: | Line 5: | ||
between them. | between them. | ||
− | The lectures are available at [http:// | + | The lectures are available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/]. |
Revision as of 02:12, 5 May 2009
Verilog is a hardware description language used to model processes in the FPGAs of several HPSDR boards.
A course was presented by Kirk Wickland. It cosisted of ten one hour recorded lectures on how to program in Verilog, including tools usage, and another five lectures on code walk-throughs for the code inside of Mercury, Penelope, Ozy, and the signal flows between them.
The lectures are available at http://verilog.openhpsdr.org/.