Difference between revisions of "Verilog"
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'''Verilog''' is a hardware description language used to model processes in the FPGAs of several HPSDR boards. | '''Verilog''' is a hardware description language used to model processes in the FPGAs of several HPSDR boards. | ||
− | A course was presented by Kirk | + | A course was presented by Kirk Weedman. It cosisted of ten one hour recorded lectures on how to program in Verilog, |
including tools usage, and another five lectures on code walk-throughs for the code inside of [[MERCURY|Mercury]], [[PENELOPE|Penelope]], [[OZY|Ozy]], and the signal flows | including tools usage, and another five lectures on code walk-throughs for the code inside of [[MERCURY|Mercury]], [[PENELOPE|Penelope]], [[OZY|Ozy]], and the signal flows | ||
between them. | between them. | ||
The lectures are available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/]. | The lectures are available at [http://verilog.openhpsdr.org/ http://verilog.openhpsdr.org/]. |
Revision as of 04:57, 5 May 2009
Verilog is a hardware description language used to model processes in the FPGAs of several HPSDR boards.
A course was presented by Kirk Weedman. It cosisted of ten one hour recorded lectures on how to program in Verilog, including tools usage, and another five lectures on code walk-throughs for the code inside of Mercury, Penelope, Ozy, and the signal flows between them.
The lectures are available at http://verilog.openhpsdr.org/.