Verilog

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Verilog is a hardware description language used to model processes in the FPGAs of several HPSDR boards.

A course was presented by Kirk Weedman. It consisted of ten one hour recorded lectures on how to program in Verilog, including tools usage, and another five lectures on code walk-throughs for the code inside of Mercury, Penelope, Ozy, and the signal flows between them. Many lectures have an additional half hour of demonstrations or examples of the programming and simulation tools in the context of the lecture's topics.

Lectures 1 through 10 are about learning to program in Verilog.

Lectures 11 through 16 are special topics, focusing on the Verilog code as used inside of Mercury, Ozy, and Penelope, issues, and improvements being developed by Kirk for communicating between the modules, which all are in separate clock domains.

The lectures are available at http://verilog.openhpsdr.org/.