Verilog
From HPSDRwiki
Verilog is a hardware description language used to model processes in the FPGAs of several HPSDR boards.
A course was presented by Kirk Wickland. It cosisted of ten one hour recorded lectures on how to program in Verilog, including tools usage, and another five lectures on code walk-throughs for the code inside of Mercury, Penelope, Ozy, and the signal flows between them.
The lectures are available at http://varilog.opensdr.org/.
