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[Xylo-SDR] More Sample Verilog - a 9850 DDS controller

Posted Verilog for a 9850 DDS Control module @ http://www.tracey.org/wjt/sdr1k/Xylo/9850Control.zip

This is a simulator only gizmo at the moment that presents a tuning and phase register that can be used to clock a tuning word into an AD9850 DDS Simulation waveform file included to see how it works in the simulator.

Next step for me on this one will be to hook it up to USB FIFO and to try it with one of the AmQRP DDS boards. Then to do a version for a pair of 9851's generating quadrature.


Bill (kd5tfd)