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[Xylo-SDR] Wolfson interface

My student has completed her VHDL interface to the Wolfson chip so I need to catch up! Attached is my Verilog version. This nearly simulates OK expect that I sometimes get an Undefined state in the state machine and can't seem to track it down. Perhaps one of the more experienced in the group could point out my error.

By looking at the RTL I have been able to get the code size down to just 1% so plenty of room in the FPGA for more features.

The code simply sends the left audio channel from the Wolfson A/D chip over FIFO 4, I then use PortAudio to play it.

Phil C - thanks for all the comments in your code, sure makes understanding it easy!

Phil... VK6APH

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