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Re: [Xylo-SDR] Clocks for USB FX2, TI PCM4202, etc.
This really does make a 'one size fit's all'! Minimizes parts count which is
what the Altera was inviting us to do!
Re the inclusion. I suggest we all use the forums to post schematics and
documentation, since the reflector (unless you are the list manager(smile))
can only 'hold' small attachments. I am working with Dale to produce a dummy
user who watches the Xylo-Phreaks area and sends posts to this list when new
posts are available there.
From: email@example.com [mailto:firstname.lastname@example.org]
On Behalf Of Don AE5K
Sent: Thursday, December 15, 2005 7:06 PM
Subject: [Xylo-SDR] Clocks for USB FX2, TI PCM4202, etc.
I've been lurking in the background like many on this list, trying to
absorb all the intelligence being thrown about... and this includes
doing some study of data sheets on some of the proposed parts.
Looking at the FX2 USB data sheet I find it needs 24.000 MHz.
Looking at the TI PCM4202 data sheet I find it needs 24.576 MHz.
And Phil H. has been looking for something higher than 24 MHz. for
Altera Cyclone FPGA clocking.
And there has been some discussion (on other lists) about the accuracy
and stability of the clocks in sound cards that we're intending to
After a little exercise with the good old calculator, I would like to
throw out a possible idea to kick around.
Attached is a PDF file of a block diagram. In case it does not make it
to you via this email, I'll also post a link to it on our Xylo-SDR web
page a little later this evening. Referring to the diagram...
I propose using a 96 MHz. oscillator. This is quite a common frequency
for some microwavers and can be optionally disciplined by the "reflock"
circuitry. (It might serve also as a multiplier chain oscillator for
those interested in 1296 and up microwave work.) The reflock can be
referenced to an available 10 MHz., 1 pps, or other stable reference
The 96 MHz. neatly divides by 4 to produce the 24.000 MHz. we need for
FX2 USB. Further dividing by 125 yields 192 Hz which is fed into a PLL
phase detector. A VCO in the PLL produces the 24.576 MHz required for
the PCM4202 (and other chips). The PCM4202, if programmed for 192 Hz
sampling, yields a nice 192 Hz. output on the LRCK (left/right clock)
which might be used in the PLL feedback to the phase detector in lieu of
an actual outboard divider.
This proposal also gives Phil H. his higher clocking frequency for the
Cyclone chip. The cyclone FPGA should be able to easily handle the
various logic necessary for the reflock, the divisions, and the PLL
except for the VCO. It also provides very accurate and stable clocking
to the parts, eliminating some of the problems caused by off frequency
clocks and wandering frequencies...especially if the reflock and a GPS
or other reference is used.
OK, shoot holes in it ... I'm learning!
PS - this discussion list is now up to 62 participants.