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Re: [Xylo-SDR] Clocks for USB FX2, TI PCM4202, etc.
There maybe an even simpler solution.
The 24.576 MHz requirement is only true if it is important that the
sampling be done at precisely 192 kHz. If you clock it at 24 MHz,
you'll get 187,500 Hz sampling (or 93,750 or 46,875). I suspect there
is no particular requirement for sampling at exactly the standard audio
rates for most of the applications that have been mentioned here.
Of course, part of the beauty of all this is that you can easily
implement in the FPGA the digital logic portion of the frequency scheme
you described. It would only consume a tiny fraction of the FPGA
resources. And also include the reflock...