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Re: [Xylo-SDR] Clocks for USB FX2, TI PCM4202, etc.
> I have heard that the internal PLL has a lot of jitter, which is
> precisely what we are trying to avoid.
I was NOT proposing using the internal PLL of the FPGA.
> Personally I think the A/D, and D/A aught to be it's own little
> universe, in it's own little card, with it's own precise clock and
> it's only link to the Xylo is the I2C bus.
A two board (or more) "product" is going to cost more, be less reliable
and will offer no advantage. I'm not talking about using the Xylo board
for the end "product" at all which I think almost everyone agrees with.
You are possibly talking development, I'm talking about the end product
in my clocking suggestion. Sorry if we're not on the same page.