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Re: [Xylo-SDR] Clocks for USB FX2, TI PCM4202, etc.
I have heard that the internal PLL has a lot of jitter, which is
precisely what we are trying to avoid.
The Xylo has two clock input so we are not stuck with one clock,
however, there are some issues that is another topic for the Xylo
phreaks on Teamspeak. From some literature I have read the FX2 and
the Xylo need to be synchronized with each other or you have
problems. What I wonder if the Xylo is synchronized to the FX2, will
that create a problem taking to the A/D's, I think the answer is NO
Personally I think the A/D, and D/A aught to be it's own little
universe, in it's own little card, with it's own precise clock and
it's only link to the Xylo is the I2C bus.
At 06:06 PM 12/15/2005, you wrote:
I've been lurking in the background like many on this list, trying to
absorb all the intelligence being thrown about... and this includes
doing some study of data sheets on some of the proposed parts.
Looking at the FX2 USB data sheet I find it needs 24.000 MHz.
Looking at the TI PCM4202 data sheet I find it needs 24.576 MHz.
And Phil H. has been looking for something higher than 24 MHz. for
Altera Cyclone FPGA clocking.
And there has been some discussion (on other lists) about the accuracy
and stability of the clocks in sound cards that we're intending to
After a little exercise with the good old calculator, I would like to
throw out a possible idea to kick around.
Attached is a PDF file of a block diagram. In case it does not make it
to you via this email, I'll also post a link to it on our Xylo-SDR web
page a little later this evening. Referring to the diagram...
I propose using a 96 MHz. oscillator. This is quite a common frequency
for some microwavers and can be optionally disciplined by the "reflock"
circuitry. (It might serve also as a multiplier chain oscillator for
those interested in 1296 and up microwave work.) The reflock can be
referenced to an available 10 MHz., 1 pps, or other stable reference
The 96 MHz. neatly divides by 4 to produce the 24.000 MHz. we need for
FX2 USB. Further dividing by 125 yields 192 Hz which is fed into a PLL
phase detector. A VCO in the PLL produces the 24.576 MHz required for
the PCM4202 (and other chips). The PCM4202, if programmed for 192 Hz
sampling, yields a nice 192 Hz. output on the LRCK (left/right clock)
which might be used in the PLL feedback to the phase detector in lieu of
an actual outboard divider.
This proposal also gives Phil H. his higher clocking frequency for the
Cyclone chip. The cyclone FPGA should be able to easily handle the
various logic necessary for the reflock, the divisions, and the PLL
except for the VCO. It also provides very accurate and stable clocking
to the parts, eliminating some of the problems caused by off frequency
clocks and wandering frequencies...especially if the reflock and a GPS
or other reference is used.
OK, shoot holes in it ... I'm learning!
PS - this discussion list is now up to 62 participants.
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"I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time ... "