Re: [Xylo-SDR] Latest S3 ADC schematic

["Phil Harman" <pvharman@arach.net.au>]

Hi Leon,

Thanks for posting your latest circuit. You may need to pass the 24.576MHz 
clock across to your FPGA. That is unless you know a way of running with out 
it - in which case please let the rest of us know how!

Presently Bill and I are using two state machines in the FPGA - one runs of 
the 24.576MHz clock and talks to the A/D converter and the other off the FX2 
clock (12/24/48MHz) and talks to the FX2. The FX2 USB connection appears to 
be very unforgiving if you don't use its clock for any USB associated tasks.

Happy New Year

Phil.... VK6APH


----- Original Message ----- 
From: "Leon Heller" <leon.heller@bulldoghome.com>
To: "Xylo-SDR Discussion" <xylo-sdr@lists.ae5k.us>
Sent: Sunday, January 01, 2006 9:16 PM
Subject: [Xylo-SDR] Latest S3 ADC schematic


> I've simplified my schematic considerably by utilising the MC33204/2 op
> amps:
>
> http://www.leonheller.com/adc2.pdf
>
> They are single-supply op amps, with rail to rail operation on both inputs
> and outputs.
>
> A happy New Year to everyone,
>
> Leon
> --
> Leon Heller, G1HSM
> leon.heller@bulldoghome.com
> http://www.geocities.com/leon_heller
>
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